Antifuse, lower cost?

Does anyone have experience with antifuse fpgas? Are they lower cost
than static ram fpgas?

Thank you,

Scott Moore

scott moore wrote:
> Does anyone have experience with antifuse fpgas? Are they lower cost
> than static ram fpgas?
>
> Thank you,
>
> Scott Moore

are they the eeprom ones, or a high current blow?

just wondering if a reverse biased very small diode potential divider
pair could charge a FET for passthrough switch on, by the division
node. a discharge on the reverse bias diode using fet gate c as energy
source, goes forward bias, and may melt open circuit fuse. achiving cut
off.

EEPROM cell best, but physical failure is potential after so many
reprogramming cycles.

a quantum tunnel PIN+ diode gate arrangement would work the best due to
electron injection being the conduction charger of the P- gate rather
than zenner breake down. this allows the substrate voltage to be
increased. but then discharging of the floating gate becomes
statistically unlikely. UV-EPROM magnetic induction discharge also
possible.

N+ doping on far gate end placed over insulator, and also p track in
the substate beloe that, allows substrate discharge of whole chip. and
p track can be volts held to reverse bias of discharge PIN+ diodes via
p track. external to chip would be a two pin header with preserve
jumper.

cheers

We do not need any speculation. Antifuse FPGAs have been around for 20
years, Actel is the oldest supplier, Quicklogic the younger one.
The antifuse is a very small (lless than one cubic micron?) speck of
silicon that is normally an insulator, but becomes permanently
conductive when a certain (rather high) voltage and current is applied.

The system advantages are "instant-on" (no configuration process),
inherent (but limited) security and a higher radiation tolerance.
The disadvantages that have relegated antifuses to a niche market, are
one-time-only (and very slow) programmability (now that designers have
become accustomed to reprogrammability, and volatility is no longer a
dirty word), the inability of complete testing, and a seemingly natural
max size limitation.

But no need for speculation, just google Actel or Quicklogic, they will
be happy to explain...
Peter Alfke
==============
jacko wrote:
> scott moore wrote:
> > Does anyone have experience with antifuse fpgas? Are they lower cost
> > than static ram fpgas?
> >
> > Thank you,
> >
> > Scott Moore
>
> are they the eeprom ones, or a high current blow?
>
> just wondering if a reverse biased very small diode potential divider
> pair could charge a FET for passthrough switch on, by the division
> node. a discharge on the reverse bias diode using fet gate c as energy
> source, goes forward bias, and may melt open circuit fuse. achiving cut
> off.
>
> EEPROM cell best, but physical failure is potential after so many
> reprogramming cycles.
>
> a quantum tunnel PIN+ diode gate arrangement would work the best due to
> electron injection being the conduction charger of the P- gate rather
> than zenner breake down. this allows the substrate voltage to be
> increased. but then discharging of the floating gate becomes
> statistically unlikely. UV-EPROM magnetic induction discharge also
> possible.
>
> N+ doping on far gate end placed over insulator, and also p track in
> the substate beloe that, allows substrate discharge of whole chip. and
> p track can be volts held to reverse bias of discharge PIN+ diodes via
> p track. external to chip would be a two pin header with preserve
> jumper.
> 
> cheers

Peter Alfke wrote:
> We do not need any speculation. Antifuse FPGAs have been around for 20
> years, Actel is the oldest supplier, Quicklogic the younger one.
> The antifuse is a very small (lless than one cubic micron?) speck of
> silicon that is normally an insulator, but becomes permanently
> conductive when a certain (rather high) voltage and current is applied.
>
> The system advantages are "instant-on" (no configuration process),
> inherent (but limited) security and a higher radiation tolerance.
> The disadvantages that have relegated antifuses to a niche market, are
> one-time-only (and very slow) programmability (now that designers have
> become accustomed to reprogrammability, and volatility is no longer a
> dirty word), the inability of complete testing, and a seemingly natural
> max size limitation.
>
> But no need for speculation, just google Actel or Quicklogic, they will
> be happy to explain...
> Peter Alfke
> ==============
> jacko wrote:
> > scott moore wrote:
> > > Does anyone have experience with antifuse fpgas? Are they lower cost
> > > than static ram fpgas?
> > >
> > > Thank you,
> > >
> > > Scott Moore
> >
> > are they the eeprom ones, or a high current blow?
> >
> > just wondering if a reverse biased very small diode potential divider
> > pair could charge a FET for passthrough switch on, by the division
> > node. a discharge on the reverse bias diode using fet gate c as energy
> > source, goes forward bias, and may melt open circuit fuse. achiving cut
> > off.
> >
> > EEPROM cell best, but physical failure is potential after so many
> > reprogramming cycles.
> >
> > a quantum tunnel PIN+ diode gate arrangement would work the best due to
> > electron injection being the conduction charger of the P- gate rather
> > than zenner breake down. this allows the substrate voltage to be
> > increased. but then discharging of the floating gate becomes
> > statistically unlikely. UV-EPROM magnetic induction discharge also
> > possible.
> >
> > N+ doping on far gate end placed over insulator, and also p track in
> > the substate beloe that, allows substrate discharge of whole chip. and
> > p track can be volts held to reverse bias of discharge PIN+ diodes via
> > p track. external to chip would be a two pin header with preserve
> > jumper.
> >
> > cheers

Peter,
Reprogrammability, and testing, aren't an issue once the design is
stable. Where I work, we use SRAM based devices to proof designs
intended for OTP targets, and once it is functional, we migrate it to
the final device. Generally speaking, we only do this for designs that
must function in high-radiation environments, or the customer is
nervous about the bitstreams not being "secure", but it isn't that
difficult to port vendor neutral code.

It's not perfect, and any problems with the migration result in
expensive duds, but we treat it kind of like an ASIC flow, so the
actual "dud rate" is very low.

This is also the primary reason why our site doesn't use any
coregen/megawizard/etc tools to generate IP. *All* of our IP must be in
the form of VHDL, or vendor-neutral netlists, such as EDIF or VQM. It
can be a pain, but all of our code can be shared without worrying about
the target device.

Well, we could get into a long discussion about relative security, and
about radiation mitigation, but this is not the right place for that.
I must, however, point out that "vendor-neutral" design pays a very
high price in not being able to take advantage of all the "goodies"
that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers,
clock manipulation and clock distribution, Serdes and 75-picosecond I/O
granularity, to name just a few that come to mind. And just wait what
we will announce in V-5LXT...)
Portability forces you to design with 15 year-old basic structures.
That's like living without indoor plumbing, electricity and telephone.
:-(
But your company seems to know why they like you to do it. Frugality
envigorates body and soul...
Peter Alfke, Xilinx
=================
radarman wrote:
> Peter Alfke wrote:
> > We do not need any speculation. Antifuse FPGAs have been around for 20
> > years, Actel is the oldest supplier, Quicklogic the younger one.
> > The antifuse is a very small (lless than one cubic micron?) speck of
> > silicon that is normally an insulator, but becomes permanently
> > conductive when a certain (rather high) voltage and current is applied.
> >
> > The system advantages are "instant-on" (no configuration process),
> > inherent (but limited) security and a higher radiation tolerance.
> > The disadvantages that have relegated antifuses to a niche market, are
> > one-time-only (and very slow) programmability (now that designers have
> > become accustomed to reprogrammability, and volatility is no longer a
> > dirty word), the inability of complete testing, and a seemingly natural
> > max size limitation.
> >
> > But no need for speculation, just google Actel or Quicklogic, they will
> > be happy to explain...
> > Peter Alfke
> > ==============
> > jacko wrote:
> > > scott moore wrote:
> > > > Does anyone have experience with antifuse fpgas? Are they lower cost
> > > > than static ram fpgas?
> > > >
> > > > Thank you,
> > > >
> > > > Scott Moore
> > >
> > > are they the eeprom ones, or a high current blow?
> > >
> > > just wondering if a reverse biased very small diode potential divider
> > > pair could charge a FET for passthrough switch on, by the division
> > > node. a discharge on the reverse bias diode using fet gate c as energy
> > > source, goes forward bias, and may melt open circuit fuse. achiving cut
> > > off.
> > >
> > > EEPROM cell best, but physical failure is potential after so many
> > > reprogramming cycles.
> > >
> > > a quantum tunnel PIN+ diode gate arrangement would work the best due to
> > > electron injection being the conduction charger of the P- gate rather
> > > than zenner breake down. this allows the substrate voltage to be
> > > increased. but then discharging of the floating gate becomes
> > > statistically unlikely. UV-EPROM magnetic induction discharge also
> > > possible.
> > >
> > > N+ doping on far gate end placed over insulator, and also p track in
> > > the substate beloe that, allows substrate discharge of whole chip. and
> > > p track can be volts held to reverse bias of discharge PIN+ diodes via
> > > p track. external to chip would be a two pin header with preserve
> > > jumper.
> > >
> > > cheers
>
> Peter,
> Reprogrammability, and testing, aren't an issue once the design is
> stable. Where I work, we use SRAM based devices to proof designs
> intended for OTP targets, and once it is functional, we migrate it to
> the final device. Generally speaking, we only do this for designs that
> must function in high-radiation environments, or the customer is
> nervous about the bitstreams not being "secure", but it isn't that
> difficult to port vendor neutral code.
>
> It's not perfect, and any problems with the migration result in
> expensive duds, but we treat it kind of like an ASIC flow, so the
> actual "dud rate" is very low.
>
> This is also the primary reason why our site doesn't use any
> coregen/megawizard/etc tools to generate IP. *All* of our IP must be in
> the form of VHDL, or vendor-neutral netlists, such as EDIF or VQM. It
> can be a pain, but all of our code can be shared without worrying about
> the target device.

Peter Alfke wrote:
> Well, we could get into a long discussion about relative security, and
> about radiation mitigation, but this is not the right place for that.
> I must, however, point out that "vendor-neutral" design pays a very
> high price in not being able to take advantage of all the "goodies"
> that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers,
> clock manipulation and clock distribution, Serdes and 75-picosecond I/O
> granularity, to name just a few that come to mind. And just wait what
> we will announce in V-5LXT...)
> Portability forces you to design with 15 year-old basic structures.
> That's like living without indoor plumbing, electricity and telephone.
> :-(
> But your company seems to know why they like you to do it. Frugality
> envigorates body and soul...
> Peter Alfke, Xilinx
> =================
Wau - does this mean that V-5LXT has some other super cool
new goodies above PCI Express MAC !?

Guess so.

Peter - you usually use simple sentences, but this time I had to look
up 2 words out of 5 word sentence, I found one at wikipedia, the other
not. I am just saying that non-english speaking people will not be able
to understand your last sentence to radarman (not even after a quick
search at wikipedia!).

Antti

Hi,

Peter Alfke schrieb:
> I must, however, point out that "vendor-neutral" design pays a very
> high price in not being able to take advantage of all the "goodies"
> that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers,
> clock manipulation and clock distribution, Serdes and 75-picosecond I/O
> granularity, to name just a few that come to mind. And just wait what
> we will announce in V-5LXT...)

Portability is freedom for the designer. I'm very lucky, that
portability is given for standard RTL-Code. No I like to have
portability for specialised features. Why can't there be one way to
instanciate RAM without dependancy on tool and target lib?
My last XCV-code is fixed to XST and won't work (easily) with Synplify.
Bad thing, if XiIlinx changes the synthesis tool again and I have to
migrate old code.
You will allways need to check, wheter a new technology provides
features necessary for your code, but I would prefer to have no problem
to transfer code for RAM of DPLLs from one vendor or tool to another.

bye Thomas

scott moore schrieb:

> Does anyone have experience with antifuse fpgas? Are they lower cost
> than static ram fpgas?

Define lower cost *g*. Cost per device? Cost from the equipment view?
You need generally more money per device for same complexity and have
additional costs for the programming. But your equipment needs only one
device, reducing costs from the equipment point of view. You need to
think about a lot of parameters, before you could say if antifuse fpgas
have lower or higher costs. I guess most designs are cheaper with
ram-based fpgas.

bye Thomas

Antti wrote:
> Peter Alfke wrote:
> 
>>Well, we could get into a long discussion about relative security, and
>>about radiation mitigation, but this is not the right place for that.
>>I must, however, point out that "vendor-neutral" design pays a very
>>high price in not being able to take advantage of all the "goodies"
>>that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers,
>>clock manipulation and clock distribution, Serdes and 75-picosecond I/O
>>granularity, to name just a few that come to mind. And just wait what
>>we will announce in V-5LXT...)
>>Portability forces you to design with 15 year-old basic structures.
>>That's like living without indoor plumbing, electricity and telephone.
>>:-(
>>But your company seems to know why they like you to do it. Frugality
>>envigorates body and soul...
>>Peter Alfke, Xilinx
>>=================
> 
> Wau - does this mean that V-5LXT has some other super cool
> new goodies above PCI Express MAC !?
> 
> Guess so.
> 
> Peter - you usually use simple sentences, but this time I had to look
> up 2 words out of 5 word sentence, I found one at wikipedia, the other
> not. I am just saying that non-english speaking people will not be able
> to understand your last sentence to radarman (not even after a quick
> search at wikipedia!).

did you try "invigorates" ?  ;)

-jg

On 8 Oct 2006 23:20:38 -0700, "Antti" <Antti.Lukats@xilant.com> wrote:

>Peter Alfke wrote:
>> Well, we could get into a long discussion about relative security, and
>> about radiation mitigation, but this is not the right place for that.
>> I must, however, point out that "vendor-neutral" design pays a very
>> high price in not being able to take advantage of all the "goodies"
>> that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers,
>> clock manipulation and clock distribution, Serdes and 75-picosecond I/O
>> granularity, to name just a few that come to mind. And just wait what
>> we will announce in V-5LXT...)
>> Portability forces you to design with 15 year-old basic structures.
>> That's like living without indoor plumbing, electricity and telephone.
>> :-(
>> But your company seems to know why they like you to do it. Frugality
>> envigorates body and soul...
>> Peter Alfke, Xilinx
>> =================
>Wau - does this mean that V-5LXT has some other super cool
>new goodies above PCI Express MAC !?
>
>Guess so.
>
>Peter - you usually use simple sentences, but this time I had to look
>up 2 words out of 5 word sentence, I found one at wikipedia, the other
>not. I am just saying that non-english speaking people will not be able
>to understand your last sentence to radarman (not even after a quick
>search at wikipedia!).
>
>Antti

I think dictionary.com is really helpful here:
http://dictionary.reference.com/browse/envigorates. You see even
people whose mother tongue is english make mistakes sometimes ;-)