FPGA to SRAM port interface

         _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _
PCLK  |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
         _______
ALE   __/       \______________________________________________________
      __________________         ___         ___         ___         __
WRITE#                  \_______/   \_______/   \_______/   \_______/

             _______  __________  __________  __________  __________
DTADD ______/ ADDR  \/  DATA0   \/  DATA1   \/  DATA2   \/  DATA3   \__
            \_______/\__________/\__________/\__________/\__________/


Mike,

PCLK is 175MHz (DSP internal peripheral clock).
I can generate a 175MHz clock, but it will probably not be in phase
with PCLK.
As you can see, WRITE# signal is low for just one clock. If I have the
bad luck of sampling it at the transition points it is possible that
I'll miss the low part of it.
A 350MHz clock is too high! Maybe something a bit higher than 175.
If the "dangerous" aproach does not work, I'll try this one.

Luiz Carlos