longest webcase record

All

I am wondering what the record is for having the longest Xilinx webcase
open .

All I asked was whether I can do boundary scan in a Coolrunner II using
sstl logic levels, over three weeks ago.

Ten days ago they answered half my question but either bsdlanno has a
serious bug or their answer was wrong.

I am left with polling xilinx every couple of days.

Colin

colin wrote:
> All
> 
> I am wondering what the record is for having the longest Xilinx webcase
> open .
> 
> All I asked was whether I can do boundary scan in a Coolrunner II using
> sstl logic levels, over three weeks ago.
> 
> Ten days ago they answered half my question but either bsdlanno has a
> serious bug or their answer was wrong.
> 
> I am left with polling xilinx every couple of days.
> 
> Colin
> 
I suggest you open a webcase to find the answer to your question.
HTH, Syms.

"colin" <colin_toogood@yahoo.com> wrote in message 
news:1160466211.076872.226570@i42g2000cwa.googlegroups.com...
> All
>
> I am wondering what the record is for having the longest Xilinx webcase
> open .
>
> All I asked was whether I can do boundary scan in a Coolrunner II using
> sstl logic levels, over three weeks ago.
>
> Ten days ago they answered half my question but either bsdlanno has a
> serious bug or their answer was wrong.
>

I've got a couple with Altera that have been open for well over a year 
now....the clock is still running.

KJ 

colin wrote:
> All
> 
> I am wondering what the record is for having the longest Xilinx webcase
> open .
> 
> All I asked was whether I can do boundary scan in a Coolrunner II using
> sstl logic levels, over three weeks ago.
> 
> Ten days ago they answered half my question but either bsdlanno has a
> serious bug or their answer was wrong.
> 
> I am left with polling xilinx every couple of days.
> 
> Colin
> 

trust me, "Open" is better than "closed" with the notation of something 
like "will be addressed in next major release".  Once they get a CR 
assigned, they go into a black hole.

Colin,

Are you trying to interface to the JTAG port using SSTL drivers and
receivers?  If so, then this is an interfacing question (and one that
can be answered in 60 seconds with a simulator), and really has nothing
to do with boundary scan at all.

If you post the part family (eg Spartan 3E), and the SSTL interface
class and supply voltages, I can run the simulation, and see if it works.

Austin

Ray Andraka wrote:
> trust me, "Open" is better than "closed" with the notation of something
> like "will be addressed in next major release".  Once they get a CR
> assigned, they go into a black hole.

I agree.  But I have an even bigger complaint about the whole webcase
system.

We use a lot of Xilinx parts, and occasionally we run into problems.
We generally only use webcase as a last resort, as I hate to clog up
their system with simple cases.  So sometimes we find a problem and a
work-around ourselves.  This information should be valuable to Xilinx,
so I open a case to tell them this.  My frustration is that the basic
response is "So you have a work-around?  Case closed!"  This info goes
into the same black hole.

My most recent example:

We are using a lot of spartan 3E parts, with the BPI mode configuration
- which is awesome for our application.  The early parts (stepping 0)
had an issue where JTAG configuration would fail if the FPGA is set to
BPI mode and the attached memory had a valid bitstream.  The datasheet
says that this has been fixed in stepping 1.  We have never had any
stepping 0 devices so we ignored this issue, but it turns out that it
is still present in stepping 1.  This wasted a lot of our time until we
figured out what was going on.  Xilinx has two suggested work arounds,
which both work, but weren't good for our application.  Now we are in
production and the JTAG interface is not needed (as it was used for
development only), so this is no longer an issue for us.  I figured
that Xilinx would like to know that this issue was not fixed in
stepping 1, and that they still have an issue with their silicon, so I
opened a webcase.  But I basically got the response I mentioned
previously:
"So this isn't a problem for you?  Case Closed!"

I opened the case in August, and the engineer ran an example design
himself and then ended the case with:

"I let the Spartan group know that this problem still exists in
Stepping 1 parts. They are looking into why this is not fixed. Since
you are ok with the workaround and expressed that this is not a
problem. I am going to go ahead and close this case. Please feel free
to open up additional cases if need be. Thank you."

No, it isn't a problem for us, anymore, but there should be some sort
of errata posted ASAP so that other customers do not run into the same
problems we did.  I gave it some time, but I still don't see anything,
so I am posting here.

Xilinx's system is broken, as they have no good means for customer
feedback.  So I am hoping that comp.arch.fpga might work better than
webcase?

Jason Daughenbaugh
http://www.advanced.pro

Austin

I have a coolrunner II with some pins which are functionaly (after
programming) SSTL. I want to perform boundary scan (interconnect)
testing and I want to know whether the CPLD will do it using SSTL or
CMOS logic levels on these pins.

I am aware that CMOS levels will work but for marketing reasons it
would be much better if they were SSTL.

I talked about BSDLANNO because xilinx support said that once a pin is
used as an input or output that is all it will do during boundary scan
but the BSDLANNO documentation and a quick experiment on my part says
otherwise. (I created a design with pinA <= pinB and created a BSDL
file)

I understand why you might think I was talking about the JTAG port
itself but curiously despite a lengthy first email in my webcase they
thought I meant the jtag port as well.

Colin

Austin Lesea wrote:
> Colin,
>
> Are you trying to interface to the JTAG port using SSTL drivers and
> receivers?  If so, then this is an interfacing question (and one that
> can be answered in 60 seconds with a simulator), and really has nothing
> to do with boundary scan at all.
>
> If you post the part family (eg Spartan 3E), and the SSTL interface
> class and supply voltages, I can run the simulation, and see if it works.
> 
> Austin

daughenbaugh@gmail.com schrieb:

> Ray Andraka wrote:
> > trust me, "Open" is better than "closed" with the notation of something
> > like "will be addressed in next major release".  Once they get a CR
> > assigned, they go into a black hole.
>
> I agree.  But I have an even bigger complaint about the whole webcase
> system.
>
> We use a lot of Xilinx parts, and occasionally we run into problems.
> We generally only use webcase as a last resort, as I hate to clog up
> their system with simple cases.  So sometimes we find a problem and a
> work-around ourselves.  This information should be valuable to Xilinx,
> so I open a case to tell them this.  My frustration is that the basic
> response is "So you have a work-around?  Case closed!"  This info goes
> into the same black hole.
>
> My most recent example:
>
> We are using a lot of spartan 3E parts, with the BPI mode configuration
> - which is awesome for our application.  The early parts (stepping 0)
> had an issue where JTAG configuration would fail if the FPGA is set to
> BPI mode and the attached memory had a valid bitstream.  The datasheet
> says that this has been fixed in stepping 1.  We have never had any
> stepping 0 devices so we ignored this issue, but it turns out that it
> is still present in stepping 1.  This wasted a lot of our time until we
> figured out what was going on.  Xilinx has two suggested work arounds,
> which both work, but weren't good for our application.  Now we are in
> production and the JTAG interface is not needed (as it was used for
> development only), so this is no longer an issue for us.  I figured
> that Xilinx would like to know that this issue was not fixed in
> stepping 1, and that they still have an issue with their silicon, so I
> opened a webcase.  But I basically got the response I mentioned
> previously:
> "So this isn't a problem for you?  Case Closed!"
>
> I opened the case in August, and the engineer ran an example design
> himself and then ended the case with:
>
> "I let the Spartan group know that this problem still exists in
> Stepping 1 parts. They are looking into why this is not fixed. Since
> you are ok with the workaround and expressed that this is not a
> problem. I am going to go ahead and close this case. Please feel free
> to open up additional cases if need be. Thank you."
>
> No, it isn't a problem for us, anymore, but there should be some sort
> of errata posted ASAP so that other customers do not run into the same
> problems we did.  I gave it some time, but I still don't see anything,
> so I am posting here.
>
> Xilinx's system is broken, as they have no good means for customer
> feedback.  So I am hoping that comp.arch.fpga might work better than
> webcase?
>
> Jason Daughenbaugh
> http://www.advanced.pro

JTAG BPI S3E issue - there is a solution that fixes the problem
the external flash memory can be put into status read mode using
CFI commands and boundary scan, then the JTAG can be used to
work with the FPGA as if there S3e bug wasnt there. Its a bit tricky
but working solution.

Antti

Antti wrote:
> JTAG BPI S3E issue - there is a solution that fixes the problem
> the external flash memory can be put into status read mode using
> CFI commands and boundary scan, then the JTAG can be used to
> work with the FPGA as if there S3e bug wasnt there. Its a bit tricky
> but working solution.

I like your solution.  Clever!

Does this mean that you ran into this problem too?  Do you see it with
Stepping 1 as well?

Jason

So, you wish to drive a LVCMOS input from a SSTL output?

If this is what you are doing, at 2.5 volts, then if the CPLD is
programed for SSTL class I, and there are no resistors used (no
terminations), then the SSTL output is compatible with the LVCMOS input.

This can be simulated with any signal integrity simulation tool (like
Mentor's Hyperlynx) in about 60 seconds (which I did).

To really know, and to be absolutely sure, I would need the part number
and manufacturer of the CPLD, and the IBIS file for the SSTL output (I
used the SSTL_I output for a V4 FPGA).

I think I understand the hotline's confusion now.  Your boundary scan
has nothing to do with JTAG.  How confusing, as the only context that we
have heard of boundary scan in, is JTAG.

Austin