Question about lib manual of Xilinx

Hi,
The following is the VHDL example on page 699, Libraries Guide, ISE
8.1i. I have two questions in this example.
1. This example is not for XST (In ISE, I can use the end port map and
include
Library UNISIM;
use UNISIM.vcomponents.all;
as provided in VHDL template).
Just for VHDL grammar, I am curious about INIT is defined a 8 bit
bit_vector, then it declares

attribute INIT : string;
attribute INIT of LUT3_instance_name : label is "8";

I cannot understand the necessary of the attribute sentences.

2. The following is wrong? I guess the values can be 0,1,2,...63.
-- values can be 0, 1, 2, 3, 4, 5, 6, 7, 8

At least it is different from the LUT1 and LUT2 examples, one of them
should be wrong.


Thank you very much.





----------------------------
VHDL Instantiation Template for LUT3
-- Component Declaration for LUT3 should be placed
-- after architecture statement but before begin keyword
component LUT3
-- synthesis translate_off
generic (
INIT : bit_vector := X"8");
-- synthesis translate_on
port (O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT3
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT3_instance_name : label is "8";
-- values can be 0, 1, 2, 3, 4, 5, 6, 7, 8
-- Component Instantiation for LUT3 should be placed
-- in architecture after the begin keyword --
LUT3_INSTANCE_NAME : LUT3
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2);