Hi there, I'm trying to decide on which FPGA vendor to use for a project out of Xilinx and Altera. The one we chose will depend on a certain memory bandwidth being met so I'm interested in the maximum supported bus widths. I'm currently heading down the RLDRAM route and have been trying to figure out how many devices are supported on the larger Virtex-4 devices. Does anyone have any experience of implementing this memory on Xilix? I've searched through the Xilinx doco and have come up with nothing concrete at all. The Altera doco clearly states the number of devices supported for each device and is generally much better quality. Any help appreciated. SJ. -- Posted via a free Usenet account from http://www.teranews.com
Supported bus widths for RLDRAM on Virtex4?
Started by ●October 25, 2006
Reply by ●October 25, 20062006-10-25
Based on the info posted on the web: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/advantages/memory_interfaces.htm http://www.xilinx.com/products/design_resources/mem_corner/index.htm The number of data pins is over 400 for RLDRAM II: 259Gbps/600bps/pin = 432. HTH, Jim http://home.comcast.net/~jimwu88/tools/ Your name wrote:> Hi there, > > I'm trying to decide on which FPGA vendor to use for a project out of > Xilinx and Altera. The one we chose will depend on a certain memory > bandwidth being met so I'm interested in the maximum supported bus widths. > > I'm currently heading down the RLDRAM route and have been trying to figure > out how many devices are supported on the larger Virtex-4 devices. Does > anyone have any experience of implementing this memory on Xilix? I've > searched through the Xilinx doco and have come up with nothing concrete at > all. The Altera doco clearly states the number of devices supported for > each device and is generally much better quality. > > Any help appreciated. SJ. > > -- > Posted via a free Usenet account from http://www.teranews.com