xilinx sync fifo with first word fall-through

I have to make a quick fix to get OPB_UARTLITE fifo larger
seems like simple thing, just replace the fifo, but xilinx coregen
is not able to create a FIFO with first word fall-through so there
latency on read and data from uart seems like delayed.

the FIFO has to use BRAM, I was hoping that coregen is easy way
but it doesnt look like. sure its not so complicated to write it from
scratch but its really boring thing todo, there should be some ready
solutions also?

target device is S3e so I cant use the V4-V5 FIFO16 that has
first word fall-through option

Antti

Antti wrote:
> I have to make a quick fix to get OPB_UARTLITE fifo larger
> seems like simple thing, just replace the fifo, but xilinx coregen
> is not able to create a FIFO with first word fall-through so there
> latency on read and data from uart seems like delayed.
>
> the FIFO has to use BRAM, I was hoping that coregen is easy way
> but it doesnt look like. sure its not so complicated to write it from
> scratch but its really boring thing todo, there should be some ready
> solutions also?
>
> target device is S3e so I cant use the V4-V5 FIFO16 that has
> first word fall-through option
>
> Antti



May be it's not pretty, but i'm using this for quite a while.
I'm creating wrapper for the fifo and this component.




-------------------------------------------------------------------------------

--	Special entity "auto_first_read"
--	provide loading output register with first word, as soon this first
word comes to Fifo. It forms additional
--	RdEn pulse and take care of proper "Empty" signal.
---------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
------------------------------
library work;
use work.types.all;
use work.components.all;

---------------------------------------------------------------------------
ENTITY auto_first_read IS
	port (
		RdEn: in std_logic;
		RdCe,RdClk: in std_logic;
		Ainit: in std_logic;
		Empty: in std_logic;
		RdEnOut: out std_logic;
		EmptyOut: out std_logic);
END auto_first_read;

ARCHITECTURE arch OF auto_first_read IS
---------------------------------------------------------------------------
	signal 		iNextState 	: integer;
	signal		iAutoRdEnOut,iStrobRdEnOut,iEmptyOut: std_logic;
	begin

---------------------------------------------------------------------------
--	This process forms "iAutoRdEnOut"-  additional pulse to pass data to
output pipeline reg
--	and "iEmptyOut" - delayed ver of "empty" signal from asyncfifo
	process (Ainit, RdClk ) begin

	if (Ainit='1')	then
		iNextState<=0;
		iAutoRdEnOut<='0'; iStrobRdEnOut<='0'; iEmptyOut<='1';
	elsif (RdClk'Event and RdClk='1') then
	  if RdCe='1' then
		iAutoRdEnOut<='0'; iStrobRdEnOut<='0'; iEmptyOut<='1';

		case iNextState is
		when 0 => -- check was something written
			if empty='0' then
				iAutoRdEnOut<='1'; 	-- this write the word into output pipeline reg
				iNextState<=iNextState+1;
			end if;
		when 1 => -- make auto read of first word
			iEmptyOut<='0'; -- this shows that fifo is not empty.
			iStrobRdEnOut<='1';
			iNextState<=iNextState+1;
		when 2 =>
			iEmptyOut<='0'; -- this shows that fifo is not empty.
			iStrobRdEnOut<='1';
			if RdEn='1' and empty='1' then
				iNextState<=0;	-- start over
				iEmptyOut<='1'; -- this shows that fifo is empty.
			end if;
		when others =>
			iNextState<=0;
		end case;
	  end if;
	end if;
	end process;


---------------------------------------------------------------------------
	RdEnOut <= (iAutoRdEnOut or (iStrobRdEnOut and RdEn)) and RdCe;
	EmptyOut<=iEmptyOut;
---------------------------------------------------------------------------
END arch;

leevv schrieb:

> May be it's not pretty, but i'm using this for quite a while.
> I'm creating wrapper for the fifo and this component.
>
{code snipped}

looks like exactly what I needed, tried last night the same but failed
with first attempt

sposiba ogromnoje!

Antti
PS I wonder how many xilinx users have made or have needed this
auto_read_first
FIFO fix? really simple thing, but not available with coregen

Antti wrote:
> leevv schrieb:
>
> > May be it's not pretty, but i'm using this for quite a while.
> > I'm creating wrapper for the fifo and this component.
> >
> {code snipped}
>
> looks like exactly what I needed, tried last night the same but failed
> with first attempt
>
> sposiba ogromnoje!
>
> Antti
> PS I wonder how many xilinx users have made or have needed this
> auto_read_first
> FIFO fix? really simple thing, but not available with coregen


Pojalujsta. ;-)

Why only xilinx. I'm just currious is it standard feature somewhere
else (A or L)?

The dedicated FIFO controller in Virtex-5 BRAMs has
First-word-fall-through as an option, and also "synchronous" (=common
read-write clock) as an option, where it avoids the re-synchronation
delay ambiguity.
Peter Alfke, Xilinx Applications

On Oct 26, 7:34 am, "leevv" <l...@mail.ru> wrote:
> Antti wrote:
> > leevv schrieb:
>
> > > May be it's not pretty, but i'm using this for quite a while.
> > > I'm creating wrapper for the fifo and this component.
>
> > {code snipped}
>
> > looks like exactly what I needed, tried last night the same but failed
> > with first attempt
>
> > sposiba ogromnoje!
>
> > Antti
> > PS I wonder how many xilinx users have made or have needed this
> > auto_read_first
> > FIFO fix? really simple thing, but not available with coregenPojalujsta. ;-)
>
> Why only xilinx. I'm just currious is it standard feature somewhere
> else (A or L)?

Peter Alfke schrieb:

> The dedicated FIFO controller in Virtex-5 BRAMs has
> First-word-fall-through as an option, and also "synchronous" (=common
> read-write clock) as an option, where it avoids the re-synchronation
> delay ambiguity.
> Peter Alfke, Xilinx Applications
>

Peter

I feel really stupid - I had to target S3e, but I dont have any nice
s3e boards around so I tested on the board that is closest to the
keyboard, what happens to be ML501.

So somehow looking at the x markings I got the impression that "first
word fall through" is not supported by coregen for S3e at all. As Pixel
Velocity just told me in email this isnt true. I was too tired eyes
hurting too much, didnt see or understand the x's in the coregen
screen.

So I have implemented Leew's solution that works just perfectly. After
that I have also validated the coregen's solution, that also works, but
has a hidden 'issue' namly with coregen FIFO 'empty' flag de-asserts
not when WR asserts but when it deasserts! so if 1000 words are written
to FIFO then empty goes away then when the WR ends eg at time when
there are 1000 words already in fifo. Leews solution doesnt have that
issue.

Ok for my current application both alternatives would work ok, but I
already had the Leew's fixup in place

Antti

Antti schrieb:

> Peter Alfke schrieb:
>
> > The dedicated FIFO controller in Virtex-5 BRAMs has
> > First-word-fall-through as an option, and also "synchronous" (=common
> > read-write clock) as an option, where it avoids the re-synchronation
> > delay ambiguity.
> > Peter Alfke, Xilinx Applications
> >
>
> Peter
>
> I feel really stupid - I had to target S3e, but I dont have any nice
[]

actually i feel less stupid, I did checkout coregen FWFT fifo
yesterday, but I used a testbench that writes a burst to the fifo, and
I looked in the simulation where the burst starts, and the FIFO output
did not change so I assumed the FIFO wasnt working - I did not notice
that the coregen FIFO delay its output update and the EMPTY flag
de-assertion until the burst ends. this can be at the same time when is
completly full, seems like a little bizarre behaviour for an FIFO. for
me it was so unexpected that I didnt investigate the coregen FWFT fifo
any longer, and implemented the workaround

Antti