Can anyone tell me what I need to drive a Camera Link output directly from a V4? I have tried LVCMOS25 and I can see differential signals at the outputs but at the end of a 2 meter cable I see only DC differential levels as if the signals are dampened somehow. Brad Smallridge aivision
Xilinx Virtex4 Outputs for Camera Link
Started by ●October 26, 2006
Reply by ●October 26, 20062006-10-26
Brad Smallridge wrote:> Can anyone tell me what I need to drive a Camera Link > output directly from a V4? I have tried LVCMOS25 and I > can see differential signals at the outputs but at the > end of a 2 meter cable I see only DC differential levels > as if the signals are dampened somehow. > > Brad Smallridge > aivisionI think the Camera Link requires a LVDS I/O standard. You may find the following link useful - http://www.alacron.com/downloads/vncl98076xz/CameraLink20v113.pdf Hope this helps.
Reply by ●October 26, 20062006-10-26
> I think the Camera Link requires a LVDS I/O standard. > > You may find the following link useful - > http://www.alacron.com/downloads/vncl98076xz/CameraLink20v113.pdf >Lattice has a reference design available for this 7:1 source synchronous LVDS interface (also known as Channel Link, Flat Link, and Camera Link). Lattice's 7:1 LVDS Video Interface Reference Design has been optimized for use with the LatticeECP2/M family of FPGAs. The reference design implements standard 7:1 LVDS interfaces using the LatticeECP2/M I/O structure. Transmit and receive interfaces are fully and efficiently implemented by specifically taking advantage of dedicated LVDS I/O, the generic DDR I/O interface, 2x gearing, and PLL clocking of edge and system clocks. The entire design has been tested using a 7:1 LVDS Display Demo system at speeds of 595MHz. Detailed Information about the Reference Design and source code is available here: http://www.latticesemi.com/products/intellectualproperty/referencedesigns/71lvdsvideointerfaceforec.cfm Hope this helps. Bart Borosky, Lattice
Reply by ●October 27, 20062006-10-27
Brad, The V4 should have no trouble whatsoever driving a 2m camera link (3M MDR type) cable. I currently have a design using a V2PRO30 that drives 5m of cable. The differential pins are driven by the below module. Take care, Rob module diff_outbuf_single(in, p_out, n_out); input in; output p_out; output n_out; OBUFDS inst1 ( .O(p_out), // Diff_p output(connect directly to top-level port) .OB(n_out), // Diff_n output (connect directly to top-level port) .I(in) // Buffer input ); endmodule "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12k1op3ddh0iea@corp.supernews.com...> Can anyone tell me what I need to drive a Camera Link > output directly from a V4? I have tried LVCMOS25 and I > can see differential signals at the outputs but at the > end of a 2 meter cable I see only DC differential levels > as if the signals are dampened somehow. > > Brad Smallridge > aivision > >
Reply by ●October 27, 20062006-10-27
> The V4 should have no trouble whatsoever driving a 2m camera link (3M MDR > type) cable.Yes I thought it was a no brainer.>I currently have a design using a V2PRO30 that drives 5m of cable. The >differential pins are driven by the below module.I think my VHDL is similar. What is your FPGA editor showing when you go to those pins? Mine shows two pads, a master and a slave. When I push into these pads I don't see any options checked. Do you have additional stuff in your UCF file? Thanks, Brad Smallridge> > Take care, > Rob > > > module diff_outbuf_single(in, p_out, n_out); > input in; > output p_out; > output n_out; > > OBUFDS inst1 ( > .O(p_out), // Diff_p output(connect directly to top-level port) > .OB(n_out), // Diff_n output (connect directly to top-level port) > .I(in) // Buffer input > ); > > endmodule > > > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > news:12k1op3ddh0iea@corp.supernews.com... >> Can anyone tell me what I need to drive a Camera Link >> output directly from a V4? I have tried LVCMOS25 and I >> can see differential signals at the outputs but at the >> end of a 2 meter cable I see only DC differential levels >> as if the signals are dampened somehow. >> >> Brad Smallridge >> aivision >> >> > >
Reply by ●October 27, 20062006-10-27
I see the same thing you do within the editor, master and slave pads. Both pads have an IO standard of LVDS_25. I have nothing else in my UCF file pertaining to these pins. Is you sure your bank voltage being powered by 2.5V? "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12k56ahdpboge63@corp.supernews.com...> >> The V4 should have no trouble whatsoever driving a 2m camera link (3M MDR >> type) cable. > > Yes I thought it was a no brainer. > >>I currently have a design using a V2PRO30 that drives 5m of cable. The >>differential pins are driven by the below module. > > I think my VHDL is similar. What is your FPGA editor showing > when you go to those pins? Mine shows two pads, a master and > a slave. When I push into these pads I don't see any options > checked. Do you have additional stuff in your UCF file? > > Thanks, > Brad Smallridge > >> >> Take care, >> Rob >> >> >> module diff_outbuf_single(in, p_out, n_out); >> input in; >> output p_out; >> output n_out; >> >> OBUFDS inst1 ( >> .O(p_out), // Diff_p output(connect directly to top-level port) >> .OB(n_out), // Diff_n output (connect directly to top-level port) >> .I(in) // Buffer input >> ); >> >> endmodule >> >> >> "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message >> news:12k1op3ddh0iea@corp.supernews.com... >>> Can anyone tell me what I need to drive a Camera Link >>> output directly from a V4? I have tried LVCMOS25 and I >>> can see differential signals at the outputs but at the >>> end of a 2 meter cable I see only DC differential levels >>> as if the signals are dampened somehow. >>> >>> Brad Smallridge >>> aivision >>> >>> >> >> > >
Reply by ●October 28, 20062006-10-28
Rob wrote:> I see the same thing you do within the editor, master and slave pads. Both > pads have an IO standard of LVDS_25. I have nothing else in my UCF file > pertaining to these pins. > > >> "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > >> news:12k1op3ddh0iea@corp.supernews.com... > >>> Can anyone tell me what I need to drive a Camera Link > >>> output directly from a V4? I have tried LVCMOS25 and I > >>> can see differential signals at the outputs but at the > >>> end of a 2 meter cable I see only DC differential levels > >>> as if the signals are dampened somehow.Brad, It is a good idea to explicitly call out IO standards in the UCF. I am a fan of determinism. The LVCMOS25 default for a differential pair *might* have to do with these signals being on low capacitance pins (denoted "_LC_" in the pinout table) which do not support LVDS outputs. If you call out LVDS in the UCF you *should* get an error if these are the type of IO pins that your signals are attached to. N.B. This is all conjecture, with the exception of the fact that the low capacitance pins do not support LVDS outputs. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.com
Reply by ●October 28, 20062006-10-28
Brad Smallridge wrote:> Can anyone tell me what I need to drive a Camera Link > output directly from a V4? I have tried LVCMOS25 and I > can see differential signals at the outputs but at the > end of a 2 meter cable I see only DC differential levels > as if the signals are dampened somehow.I'm assuming that you meant the LVDS_25 driver. Don't forget the LVDSEXT_25, which is meant for longer cable driving. --- Joe Samson Pixel Velocity
Reply by ●October 28, 20062006-10-28
Yipes, duh. My problem is that I don't understand this cable and my lines are mirrored. Thanks, though, for all your help. I am sure it will work when I connect the right signals. Say, I was getting good results from a double edge clock input circuit and a single DCM generating 140 MHz (40MHz xclk). The trick was to select a shifted output depending on the fast clock. I was unable, however, to use a double edge clock circuit on the output. The OSERDES does not have a 7x option and when you try 8x you get 8x data bits no matter how you drive the clkdiv input. Do you have anysuggestions here? Brad Smallridge aivision "Erik Widding" <widding@birger.com> wrote in message news:1162047692.852989.299520@h48g2000cwc.googlegroups.com...> Rob wrote: >> I see the same thing you do within the editor, master and slave pads. >> Both >> pads have an IO standard of LVDS_25. I have nothing else in my UCF file >> pertaining to these pins. >> >> >> "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message >> >> news:12k1op3ddh0iea@corp.supernews.com... >> >>> Can anyone tell me what I need to drive a Camera Link >> >>> output directly from a V4? I have tried LVCMOS25 and I >> >>> can see differential signals at the outputs but at the >> >>> end of a 2 meter cable I see only DC differential levels >> >>> as if the signals are dampened somehow. > > Brad, > > It is a good idea to explicitly call out IO standards in the UCF. I am > a fan of determinism. The LVCMOS25 default for a differential pair > *might* have to do with these signals being on low capacitance pins > (denoted "_LC_" in the pinout table) which do not support LVDS outputs. > If you call out LVDS in the UCF you *should* get an error if these are > the type of IO pins that your signals are attached to. > > N.B. This is all conjecture, with the exception of the fact that the > low capacitance pins do not support LVDS outputs. > > > Regards, > Erik. > > --- > Erik Widding > President > Birger Engineering, Inc. > > (mail) 100 Boylston St #1070; Boston, MA 02116 > (voice) 617.695.9233 > (fax) 617.695.9234 > (web) http://www.birger.com >
Reply by ●October 28, 20062006-10-28
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12k72t98o3ahrcc@corp.supernews.com...> > I was unable, however, to use a double edge clock circuit > on the output. The OSERDES does not have a 7x option and > when you try 8x you get 8x data bits no matter how you > drive the clkdiv input.Hi Brad, (You can now spend all evening wondering where I know you from...) I can't shed any light on your Virtex problems, but I am interested as to what leads you to bother with trying to do CameraLink with an FPGA, rather than just using the appropriate NatSemi ChannelLink chip (I'm too lazy to look up the number, but you know the one I mean.) When everything about CameraLink is designed around those interface chips, it has always seemed to me like unnecessarily hard work to reimplement their behaviour elsewhere. Is it cost, space or a sense of adventure which pushes you away from them in this design? Cheers, Will