Hi, I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke the Virtex-II series they now offer the possibility to route various clock signals to several domains on the FPGA and select them locally by specific clock multiplexer inputs. Because of the restricted amount of available pins on the device I selected (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input on each side of the FPGA, thereby saving clock multiplexer inputs which I can use as normal GPIOs, and use an external clock multiplexer instead for my 3 clocks. Has anyone made experience with such or similar solution? Has anyone used an external clock multiplexer device for frequencies up to 500 MHz, yet? Is there any recommendation which chip I could use for this application in terms of jitter, etc.? And by the way... is my approach advisable, at all? Any comments are appreciated. Regards Elmo
clock multiplexor device
Started by ●October 30, 2006
Reply by ●October 30, 20062006-10-30
If you're doing this because you don't have another two available pins on the FPGA, you need a bigger FPGA, or save pins somewhere else. I would not go into a board design using more than 90-95% of the pins on the FPGA. Now if I was updating a mature design or something like that, I might allow that margin to get a little tighter. The flexibility and reliability of doing this sort of thing, especially with clocks, inside the FPGA (where the STA tools can manage your timing) is far superior to trying to do it with an extra component on the board. Andy Elmo Fuchs wrote:> Hi, > > I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke > the Virtex-II series they now offer the possibility to route various clock > signals to several domains on the FPGA and select them locally by specific > clock multiplexer inputs. > Because of the restricted amount of available pins on the device I selected > (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input > on each side of the FPGA, thereby saving clock multiplexer inputs which I > can use as normal GPIOs, and use an external clock multiplexer instead for > my 3 clocks. > Has anyone made experience with such or similar solution? Has anyone used an > external clock multiplexer device for frequencies up to 500 MHz, yet? Is > there any recommendation which chip I could use for this application in > terms of jitter, etc.? And by the way... is my approach advisable, at all? > > Any comments are appreciated. > > Regards Elmo
Reply by ●October 30, 20062006-10-30
"Elmo Fuchs" <maerchenprinz@arcor.de> wrote in message news:4545fdf6$0$5712$9b4e6d93@newsspool3.arcor-online.net...> > Because of the restricted amount of available pins on the device I > selected > (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock > input > on each side of the FPGA, thereby saving clock multiplexer inputs which I > can use as normal GPIOs, and use an external clock multiplexer instead for > my 3 clocks. > Has anyone made experience with such or similar solution? Has anyone used > an > external clock multiplexer device for frequencies up to 500 MHz, yet? Is > there any recommendation which chip I could use for this application in > terms of jitter, etc.? And by the way... is my approach advisable, at all? > > Any comments are appreciated. > > Regards Elmo >Hi Elmo, Firstly, I recommend you appreciate Andy's comments. :-) I detect a voice of experience in his good advice! Then, when you decide to carry on with your original plan regardless, Google this:- "Runt Pulse Eliminator" site:micrel.com HTH, Syms.