reset

I am using Altera Stratix II FPGA and also power supervisor circuit
which generates reset which it tied to  nCONFIG for configuration of
the FPGA. Now, I'd like to generate RESET for the FPGA after the
configuration and  Initialization is complete everytime. I can't find a
part that can do that..any suggetions?

There are many ways to do this--here's one idea:

You can use the conf_done pin to trigger a reset chip (maxim/dallas has 
plenty of choices) and tie it to the appropriate pin on the FPGA, probably 
the DEV_CLRn (device wide asynchronous reset).



<martstev@gmail.com> wrote in message 
news:1162498322.376240.187270@e3g2000cwe.googlegroups.com...
>I am using Altera Stratix II FPGA and also power supervisor circuit
> which generates reset which it tied to  nCONFIG for configuration of
> the FPGA. Now, I'd like to generate RESET for the FPGA after the
> configuration and  Initialization is complete everytime. I can't find a
> part that can do that..any suggetions?
> 

martstev@gmail.com wrote:
> I am using Altera Stratix II FPGA and also power supervisor circuit
> which generates reset which it tied to  nCONFIG for configuration of
> the FPGA. Now, I'd like to generate RESET for the FPGA after the
> configuration and  Initialization is complete everytime. I can't find a
> part that can do that..any suggetions?
> 

or use something like

	ff_resetn:process(boot_clk)
	begin
		if (boot_clk'event and boot_clk='1') then
			if (reset_cnt/="111") then
				reset_cnt<=reset_cnt + 1;
			end if;
			reset_n<=(reset_cnt(2) AND reset_cnt(1) AND 		reset_cnt(0));
		end if;
	end process;

	ff_reset:process(boot_clk)
	begin
		if (boot_clk'event and boot_clk='1') then
			reset<=not reset_n;
		end if;
	end process;

>
> or use something like
>
> 	ff_resetn:process(boot_clk)
> 	begin
> 		if (boot_clk'event and boot_clk=3D'1') then
> 			if (reset_cnt/=3D"111") then
> 				reset_cnt<=3Dreset_cnt + 1;
> 			end if;
> 			reset_n<=3D(reset_cnt(2) AND reset_cnt(1) AND 		reset_cnt(0));
> 		end if;
> 	end process;
>
> 	ff_reset:process(boot_clk)
> 	begin
> 		if (boot_clk'event and boot_clk=3D'1') then
> 			reset<=3Dnot reset_n;
> 		end if;
> 	end process;

How do you know which value "reset_cnt" will start with after
configuration ?
Rgds
Andr=E9

martstev@gmail.com wrote:
> I am using Altera Stratix II FPGA and also power supervisor circuit
> which generates reset which it tied to  nCONFIG for configuration of
> the FPGA. Now, I'd like to generate RESET for the FPGA after the
> configuration and  Initialization is complete everytime. I can't find a
> part that can do that..any suggetions?

If you are reconfiguring the part on reset, why do you want to reset
the design again? The design will come up in the "reset" state after
configuration. Perhaps I'm missing something, but it seems redundant to
async reset an FPGA right after configuration?

ALuPin@web.de wrote:
>> or use something like
>>
>> 	ff_resetn:process(boot_clk)
>> 	begin
>> 		if (boot_clk'event and boot_clk='1') then
>> 			if (reset_cnt/="111") then
>> 				reset_cnt<=reset_cnt + 1;
>> 			end if;
>> 			reset_n<=(reset_cnt(2) AND reset_cnt(1) AND 		reset_cnt(0));
>> 		end if;
>> 	end process;
>>
>> 	ff_reset:process(boot_clk)
>> 	begin
>> 		if (boot_clk'event and boot_clk='1') then
>> 			reset<=not reset_n;
>> 		end if;
>> 	end process;
> 
> How do you know which value "reset_cnt" will start with after
> configuration ?
> Rgds
> Andr&#4294967295;
> 

you just write

signal reset_cnt : std_logic_vector(2 downto 0) := (others=>'0');

so that when the FPGA is configured it always starts at 0

No.

 := (others=>'0');

in signal declarations are not synthesizable.

Rgds

<ALuPin@web.de> wrote in message 
news:1162800744.822146.61370@f16g2000cwb.googlegroups.com...
> No.
>
> := (others=>'0');
>
> in signal declarations are not synthesizable.
>
> Rgds

Whether or not it is synthesizable depends on the synthesis tool and the 
target device.  Specifying the power up default value for the output of a 
clocked register certainly can be synthesizable.  In fact both brand 'A' and 
brand 'X' (and I'm sure others) FPGAs do specify that registers are reset at 
the completion of configuration which is the FPGA equivalent of 'power up' 
so the construct certainly is synthesizable.

One should tread with care though and probably limit the usage of default 
values to only those signals that have to do directly with generating the 
internal reset signal as was mentioned earlier in the post.  One should 
probably also only try to only use a default value of '0' as well since most 
(all?) FPGAs will clear the flip flops not set some of them to '0' and 
others to '1'.  There is a very simple technique that can be used that would 
allow a default value of '1' to be specified in the code even though the 
flip flop resets to '0' but then you'll be counting on the synthesis tool to 
implement this.

KJ 

KJ wrote:
> 
> One should tread with care though and probably limit the usage of default 
> values to only those signals that have to do directly with generating the 
> internal reset signal as was mentioned earlier in the post.  One should 
> probably also only try to only use a default value of '0' as well since most 
> (all?) FPGAs will clear the flip flops not set some of them to '0' and 
> others to '1'.  There is a very simple technique that can be used that would 
> allow a default value of '1' to be specified in the code even though the 
> flip flop resets to '0' but then you'll be counting on the synthesis tool to 
> implement this.

The synthesis tools I have used correctly synthesize even non '0' 
declaration initializations, and X does support non '0' initialization. 
And this is very handy in a lot of places. For example, I often use this 
to set the default value of registers, since I know that software will 
not attempt to change the registers until long after the FPGA has 
initialized.

radarman wrote:
> martstev@gmail.com wrote:
> > I am using Altera Stratix II FPGA and also power supervisor circuit
> > which generates reset which it tied to  nCONFIG for configuration of
> > the FPGA. Now, I'd like to generate RESET for the FPGA after the
> > configuration and  Initialization is complete everytime. I can't find a
> > part that can do that..any suggetions?
>
> If you are reconfiguring the part on reset, why do you want to reset
> the design again? The design will come up in the "reset" state after
> configuration. Perhaps I'm missing something, but it seems redundant to
> async reset an FPGA right after configuration?

One case might be when you want the reset behaviour to set a flip flop
to '1' instead of '0' (like in a one hot state machine encoding) and
the synthesis tool/target device combo doesn't happen to support this.
If you have this, then the problem is with the synthesis tool (so open
a service request and raise your beef) but in the mean time you need a
work around.  So if you happen to have that particular scenario, but
your device globally clears all flip flops to 0 then you could use the
"reset to 0 coming out of configuration" to create an internal reset
signal for the rest of the design.  Then you use that internal reset
signal to put the entire design into the state that you want as
specified by your HDL instead of as specified by the device
manufacturer.

KJ