FSL microblaze to co-processor write problem...

Hi guys,
I'm trying to connect a simple co-processor to microblaze. The
co-processor simply gets 8 inputs and does a simple arithmetic and
gives one output. The problem that I'm currently experiencing is (I
figured it out during simulation) that, when I put a data from
microblaze on FSL the fsl_m_write signal from microblaze doesn't become
1. So the co-processor never notices that there are data on the bus and
it never changes status. As well when I check the data on the FSL
microblaze-to-coprocessor bus, it is not what I'm trying to write. Put
instruction takes 2 cycles to execute. The first cycle the data on FSL
master output of microblaze is insane but the second cycle it becomes
one. However I've made sure that FSL_M_FULL is not 1. So my FIFO is
empty. The clk and reset signal of the co-processor is correctly
connected to the processor. As well I'm doing blocking read and write.
Do you have any idea why it is not working?

I've attached part of my system.v file. As far as I know all the
connections are correct. (I used co-processor wizard from EDK to
connect my co-processor to microblaze).

By the way just before attaching the code to here I checked to make
sure that clock and reset connection is OK. Previously during
simulation I checked the clock and reset and they were working fine.
However now in the system.v file as you can see below there is no clock
signal given as the input to fsl of microblaze or co-processor. However
it is working fine during simulation. I tried to set the clock port to
sys_clk_s but it seems that it has serious problem. Because my
simulation is working as if the fsl buses and peripheral is not
clocked.(ilmb_LMB_ABUS and microblaze/fsl_m_data become high
impedance).

I really appreciate your help,

Amir

microblaze ....

      .FSL0_S_CLK (  ),
      .FSL0_S_READ ( custom_ip_0_to_microblaze_0_FSL_S_Read ),
      .FSL0_S_DATA ( custom_ip_0_to_microblaze_0_FSL_S_Data ),
      .FSL0_S_CONTROL ( custom_ip_0_to_microblaze_0_FSL_S_Control ),
      .FSL0_S_EXISTS ( custom_ip_0_to_microblaze_0_FSL_S_Exists ),
      .FSL0_M_CLK (  ),
      .FSL0_M_WRITE ( microblaze_0_to_custom_ip_0_FSL_M_Write ),
      .FSL0_M_DATA ( microblaze_0_to_custom_ip_0_FSL_M_Data ),
      .FSL0_M_CONTROL ( microblaze_0_to_custom_ip_0_FSL_M_Control ),
      .FSL0_M_FULL ( microblaze_0_to_custom_ip_0_FSL_M_Full ),

////////////

  custom_ip_0_to_microblaze_0_wrapper
    custom_ip_0_to_microblaze_0 (
      .FSL_Clk ( sys_clk_s ),
      .SYS_Rst ( sys_rst_s ),
      .FSL_Rst ( custom_ip_0_to_microblaze_0_OPB_Rst ),
      .FSL_M_Clk ( net_gnd0 ),
      .FSL_M_Data ( custom_ip_0_to_microblaze_0_FSL_M_Data ),
      .FSL_M_Control ( custom_ip_0_to_microblaze_0_FSL_M_Control ),
      .FSL_M_Write ( custom_ip_0_to_microblaze_0_FSL_M_Write ),
      .FSL_M_Full ( custom_ip_0_to_microblaze_0_FSL_M_Full ),
      .FSL_S_Clk ( net_gnd0 ),
      .FSL_S_Data ( custom_ip_0_to_microblaze_0_FSL_S_Data ),
      .FSL_S_Control ( custom_ip_0_to_microblaze_0_FSL_S_Control ),
      .FSL_S_Read ( custom_ip_0_to_microblaze_0_FSL_S_Read ),
      .FSL_S_Exists ( custom_ip_0_to_microblaze_0_FSL_S_Exists ),
      .FSL_Full (  ),
      .FSL_Has_Data (  )
    );

  custom_ip_0_wrapper
    custom_ip_0 (
      .FSL_Clk ( sys_clk_s ),
      .FSL_Rst ( custom_ip_0_to_microblaze_0_OPB_Rst ),
      .FSL_S_Clk (  ),
      .FSL_S_Read ( microblaze_0_to_custom_ip_0_FSL_S_Read ),
      .FSL_S_Data ( microblaze_0_to_custom_ip_0_FSL_S_Data ),
      .FSL_S_Control ( microblaze_0_to_custom_ip_0_FSL_S_Control ),
      .FSL_S_Exists ( microblaze_0_to_custom_ip_0_FSL_S_Exists ),
      .FSL_M_Clk (  ),
      .FSL_M_Write ( custom_ip_0_to_microblaze_0_FSL_M_Write ),
      .FSL_M_Data ( custom_ip_0_to_microblaze_0_FSL_M_Data ),
      .FSL_M_Control ( custom_ip_0_to_microblaze_0_FSL_M_Control ),
      .FSL_M_Full ( custom_ip_0_to_microblaze_0_FSL_M_Full )
    );

  microblaze_0_to_custom_ip_0_wrapper
    microblaze_0_to_custom_ip_0 (
      .FSL_Clk ( sys_clk_s ),
      .SYS_Rst ( sys_rst_s ),
      .FSL_Rst (  ),
      .FSL_M_Clk ( net_gnd0 ),
      .FSL_M_Data ( microblaze_0_to_custom_ip_0_FSL_M_Data ),
      .FSL_M_Control ( microblaze_0_to_custom_ip_0_FSL_M_Control ),
      .FSL_M_Write ( microblaze_0_to_custom_ip_0_FSL_M_Write ),
      .FSL_M_Full ( microblaze_0_to_custom_ip_0_FSL_M_Full ),
      .FSL_S_Clk ( net_gnd0 ),
      .FSL_S_Data ( microblaze_0_to_custom_ip_0_FSL_S_Data ),
      .FSL_S_Control ( microblaze_0_to_custom_ip_0_FSL_S_Control ),
      .FSL_S_Read ( microblaze_0_to_custom_ip_0_FSL_S_Read ),
      .FSL_S_Exists ( microblaze_0_to_custom_ip_0_FSL_S_Exists ),
      .FSL_Full (  ),
      .FSL_Has_Data (  )

On 4 Nov 2006 09:31:57 -0800, "Xesium"
<amirhossein.gholamipour@gmail.com> wrote:

>Hi guys,
>I'm trying to connect a simple co-processor to microblaze. The
>co-processor simply gets 8 inputs and does a simple arithmetic and
>gives one output. The problem that I'm currently experiencing is (I
>figured it out during simulation) that, when I put a data from
>microblaze on FSL the fsl_m_write signal from microblaze doesn't become
>1. So the co-processor never notices that there are data on the bus and
>it never changes status. As well when I check the data on the FSL
>microblaze-to-coprocessor bus, it is not what I'm trying to write. Put
>instruction takes 2 cycles to execute. The first cycle the data on FSL
>master output of microblaze is insane but the second cycle it becomes
>one. However I've made sure that FSL_M_FULL is not 1. So my FIFO is
>empty. The clk and reset signal of the co-processor is correctly
>connected to the processor. As well I'm doing blocking read and write.
>Do you have any idea why it is not working?
<...>

I am not sure on how you do this on verilog (never workes with it!),
but I know for sure you must tell the micrtoblaze instance to really
have an fsl port (in VHDL: generic map (... C_FSL_LINKS=> 1..)

Have you done so? Because, although all pins are there, the fsl
connection will not be instantiated if you don't tell the synthesiser
to do so


best regards,

Zara

I actually connected the co-processor to the microblaze using EDK
co-processor wizard. However furthermore I checked system.mhs file.
There is a line stating:

 PARAMETER C_FSL_LINKS = 1

So I think I can assume that the FSL is connected to the microblaze.

As well in my top module file which is system.v as I've copied in my
previous post, fsl connections for microblaze_to_customip and
customip_to_microblaze have been instantiated. So I think that there
shouldn't be a problem in connection.
At least this is my impression.


Zara wrote:
> On 4 Nov 2006 09:31:57 -0800, "Xesium"
> <amirhossein.gholamipour@gmail.com> wrote:
>
> >Hi guys,
> >I'm trying to connect a simple co-processor to microblaze. The
> >co-processor simply gets 8 inputs and does a simple arithmetic and
> >gives one output. The problem that I'm currently experiencing is (I
> >figured it out during simulation) that, when I put a data from
> >microblaze on FSL the fsl_m_write signal from microblaze doesn't become
> >1. So the co-processor never notices that there are data on the bus and
> >it never changes status. As well when I check the data on the FSL
> >microblaze-to-coprocessor bus, it is not what I'm trying to write. Put
> >instruction takes 2 cycles to execute. The first cycle the data on FSL
> >master output of microblaze is insane but the second cycle it becomes
> >one. However I've made sure that FSL_M_FULL is not 1. So my FIFO is
> >empty. The clk and reset signal of the co-processor is correctly
> >connected to the processor. As well I'm doing blocking read and write.
> >Do you have any idea why it is not working?
> <...>
>
> I am not sure on how you do this on verilog (never workes with it!),
> but I know for sure you must tell the micrtoblaze instance to really
> have an fsl port (in VHDL: generic map (... C_FSL_LINKS=> 1..)
>
> Have you done so? Because, although all pins are there, the fsl
> connection will not be instantiated if you don't tell the synthesiser
> to do so
> 
> 
> best regards,
> 
> Zara