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Newbie VHDL issue with CPLD

Started by David T. December 31, 2003
I am trying to use a CPLD as a bus decoder and also have the device
latch 6 bits of data back to the host via a shared data bus. I cannot
get this code to simulate, using Xilinx Webpack. I have asked the
local Xilinx FAE for help but he is not versed in VHDL. This can't be
as difficult as it seems... nobody would be using these devices. I am
getting the following signal for most all of the signals that I have
declared. I have patterned my code after one of the examples included
in WebPack(Xilinx software).

WARNING:Xst:646 - Signal <dat_out<0>> is assigned but never used.

I have included my code... it is not that large. 
I would appreciate a kick in the right direction.

Thanks,
David Thurlow

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


--		DESCRIPTION:
--			Decode/Respond to specific addressed commands
--		   from the Host, via the BUS.
--			The commands control the FIFOs... READ/WRITE and
--		   also send Status Bits back to the Host.
--			
--
-- ************************************************************

entity decoder is
    Port (ADDR : in std_logic_vector(9 downto 0);	 -- ADDRESS BUS 
        D   : out std_logic_vector(5 downto 0);    -- OUTPUT BITS 6 OF
THEM
        N_GWR : in std_logic; 			-- BUS WRITE PULSE
        N_GRD : in std_logic;			-- BUS READ PULSE
	N_DRV_ENAB: out std_logic;	-- ENABLE THE 245 DRIVERS
        PCK_READY: in std_logic;        -- MESSAGE TO HOST READY
	DIR : out std_logic;		-- DIRECTION SEL FOR 245 DRIVERS
	IN_FIFO_EMPTY : in std_logic;	-- FIFO EMPTY SIGNAL
	OUT_FIFO_EMPTY : in std_logic;	-- FIFO EMPTY SIGNAL
	N_RST_IN : out std_logic;	-- RESET IN FIFOS
	N_RST_OUT : out std_logic;	-- RESET OUT FIFOS
	N_RST_SYS : in std_logic;	-- MASTER RESET
	N_X_RD : out std_logic;		-- HOST READS THE FIFOS
	N_X_WR : out std_logic;		-- HOST WRITES TO FIFOS
	FIRST :	out std_logic; 	     -- SET BIT 9 IN FIFOa... 1st BYTE
	LAST : 	out std_logic;	     -- SET BIT 9 IN FIFOb... last BYTE
	G_BUS_ACTIVE : out std_logic;	-- LIGHT LED DURING HOST CMDS
	TRI_STATE : out std_logic;     -- CONTROL GTS1...address selected
	TRI_STATE_IN : in std_logic);	-- CONTROL TRI-STATE OUTPUTS
end decoder;

architecture Glonet_Decode of decoder is
	-- the READx and WRITEx signals will be set when a proper
	-- address and either /GRD or /GWR are active. They will be
	-- cleared when /GRD or /GWR are inactive.
   signal DAT_OUT : std_logic_vector(5 downto 0); -- STORE STATUS
FLAGS
   signal READ0 : std_logic;   -- FLAG TO INDICATE VALID ADDRESS AND
/GRD
   signal READ1 : std_logic;  -- FLAG TO INDICATE VALID ADDRESS AND
/GRD
   signal WRITE0 : std_logic;  -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
   signal WRITE1 : std_logic;  -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
   signal WRITE2 : std_logic;  -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
   signal WRITE3 : std_logic;  -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
begin

process(N_GRD, N_GWR)  	-- THESE SIGNALS ARE THE TRIGGER FOR ANY
ACTION

begin
	-- IF A READ WAS COMMANDED, CHECK THE ADDRESS.
	-- ONLY RESPOND TO SPECIFIC ADDRESSES.
	-- SET 'FUNCTION' FLAG AND BUSY FLAG
   if N_GRD'event  and N_GRD = '0'  THEN    -- IF HOST READ AND NOT
BUSY
	case ADDR is 
	   when "0001110000" =>	-- IF 1C0h READ FIFOs
	      READ0 <= '1'; 	-- SET FUNCTION FLAG FOR USE LATER
	   when "0001110001" =>	-- IF 1C1h READ THE STATUS FLAG LATCH
	      READ1 <= '1';	-- SET FUNCTION FLAG
	   when others =>	-- READ PULSE NOT FOR US, IGNORE IT     
	   end case;
        END IF;

    if N_GWR'event and N_GWR = '0' THEN	-- IF HOST WRITE AND NOT BUSY
	case ADDR is
	   when "0001110000" =>	-- 1C0h	WRITE TO FIFOs
		WRITE0 <= '1';
	   when "0001110001" =>	-- 1C1h	WRITE TO FIFOs
		WRITE1 <= '1';
	   when "0001110010" =>	-- 1C2h	WRITE TO FIFOs
		WRITE2 <= '1';
	   when "0001110011" =>	-- 1C3h	RESET FIFOs 
		WRITE3 <= '1';
	   when others =>	-- WRITE PULSE NOT FOR US, IGNORE IT
	   end case;
        END IF;

   if N_GRD = '1' and  N_GWR = '1' then   -- NOTHING HAPPENING ON BUS
	N_X_RD <= '1';			-- DISABLE IN_FIFO READS
	N_DRV_ENAB <= '1';	-- DISABLE THE '245 DRIVERS
	N_X_WR <= '1';		-- DISABLE OUT_FIFO WRITES
	TRI_STATE <= '1';	-- TRI-STATE THE LATCHED BITS
	FIRST <= '0';		-- RESET FLAG
	LAST <= '0';		-- RESET FLAG
	G_BUS_ACTIVE <= '1';	-- TURN OFF BUS ACTIVITY FLAG
	END IF;

   if N_GRD = '1' then 		-- NO HOST READ PULSE
	READ0 <= '0';		-- RESET BOTH FLAGS
	READ1 <= '0';
	END IF;

   if N_GWR = '1' then		-- NO HOST WRITE PULSE
	WRITE0 <= '0';		-- RESET ALL WRITE FLAGS
	WRITE1 <= '0';
	WRITE2 <= '0';
	WRITE3 <= '0';
	END IF;
END PROCESS;

PROCESS(READ0,READ1,WRITE0,WRITE1,WRITE2,WRITE3,IN_FIFO_EMPTY,
OUT_FIFO_EMPTY)
begin
  -- **********************************************************************
  --       FUNCTION FLAGS!!!!
  -- **********************************************************************
   if READ0 = '1' then		-- LET HOST READ FIFOs
	DIR <= '1';		-- SET '245s TO SEND DIRECTION
	N_X_RD <= '0';		-- HAVE THE FIFOs SPIT OUT A BYTE
	N_DRV_ENAB <= '0';	-- ENABLE THE '245 OUTPUTS
	G_BUS_ACTIVE <= '0';	-- TURN ON LED
	END IF;

   if READ1 = '1' then		-- LET HOST READ THE LATCHED STATUS FLAGS
	DAT_OUT(0) <= PCK_READY;	-- SET DATA TO LATCHED OUTPUTS
	DAT_OUT(1) <= IN_FIFO_EMPTY;
	DAT_OUT(2) <= OUT_FIFO_EMPTY;
	D <= DAT_OUT;
	DIR <= '1';		-- SET '245s TO SEND DIRECTION
	TRI_STATE <= '0';	-- ENABLE DATA TO OUTPUT LATCHES
	N_DRV_ENAB <= '0';	-- ENABLE THE '245 OUTPUTS
	G_BUS_ACTIVE <= '0';	-- TURN ON LED
	END IF;

   if WRITE0 = '1' then		-- HOST WRITES TO FIFOs
	N_X_WR <= '0';		-- ENABLE FIFOs FOR WRITING
	DIR <= '0';		-- SET '245s TO RECEIVE DIRECTION
	N_DRV_ENAB <= '0';	-- ENABLE THE '245 OUTPUTS
	G_BUS_ACTIVE <= '0';	-- TURN ON LED
	END IF;

   if WRITE1 = '1' then		-- HOST WRITES TO FIFOs W/First FLAG
      FIRST <= '1';		-- FLAG TO INDICATE FIRST BYTE OF MESSAGE
      N_X_WR <= '0';		-- ENABLE FIFOs FOR WRITING
      DIR <= '0';		-- SET '245s TO RECEIVE DIRECTION
      N_DRV_ENAB <= '0';	-- ENABLE THE '245 OUTPUTS
      G_BUS_ACTIVE <= '0';	-- TURN ON LED
      END IF;

   if WRITE2 = '1' then	   -- HOST WRITES TO FIFOs W/Last FLAG
	LAST <= '1';	   -- FLAG TO INDICATE LAST BYTE OF MESSAGE
	N_X_WR <= '0';	   -- ENABLE FIFOs FOR WRITING
	DIR <= '0';	       -- SET '245s TO RECEIVE DIRECTION
	N_DRV_ENAB <= '0';	-- ENABLE THE '245 OUTPUTS
	G_BUS_ACTIVE <= '0';	-- TURN ON LED
	END IF;

   if WRITE3 = '1' then	   -- HOST RESETS FIFOs  ?? WE MAY NOT USE
THIS !!
	G_BUS_ACTIVE <= '0';		-- TURN ON LED
	END IF;

END PROCESS;

process(N_RST_SYS)
begin
    -- ******************************************************************
    --  RESET: DEFAULT SETTINGS FOR DEVICE
    -- ******************************************************************
   if N_RST_SYS = '0' then	-- SYSTEM RESET
	N_RST_IN <= '0';	-- RESET THE INPUT FIFOs
	N_RST_OUT <= '0';	-- RESET THE OUTPUT FIFOs
	N_DRV_ENAB <= '1';	-- DISABLE THE '245s
	N_X_RD <= '1';		-- DISABLE THE FIFOs
	N_X_WR <= '1';		-- 
	FIRST <= '0';		-- CLEAR FLAGS
	LAST <= '0';		--
	G_BUS_ACTIVE <= '1';	-- SHUT OF LED
	TRI_STATE <= '1';	-- TRISTATE OUTPUTS TO SHARED BUS
	READ0 <= '0';	     -- RESET ALL STATUS FLAGS
	READ1 <= '0';		--
	WRITE0 <= '0';		--
	WRITE1 <= '0';		--
	WRITE2 <= '0';		--
	WRITE3 <= '0';		--
	DAT_OUT <= "000000";	-- RESET ALL FLAGS TO ZERO
   ELSE
	N_RST_IN <= '1';	--  FIFOs
	N_RST_OUT <= '1';	--
        END IF;							
END PROCESS;					  	
end Glonet_Decode;
You are assigning DAT_OUT in two different processes. Your latch surely daoes
not
work the way you want. Additionally I would assume a Tri-State drive for "D"
when connected to the data bus.

  if N_RST_SYS = '0' then      -- SYSTEM RESET
        DAT_OUT <= (others => '0');
 elsif (YOUR LATCH TRANSPARENT CONDITION)
        DAT_OUT(0) <= PCK_READY;        -- SET DATA TO LATCHED OUTPUTS
        DAT_OUT(1) <= IN_FIFO_EMPTY;
        DAT_OUT(2) <= OUT_FIFO_EMPTY; end if;
  end if;

  D <= DAT_OUT when (YOUR READ CONDITION) else (others => 'Z');

This surely applies to other signals either.

Regards
Thomas


"David T." wrote:

> I am trying to use a CPLD as a bus decoder and also have the device > latch 6 bits of data back to the host via a shared data bus. I cannot > get this code to simulate, using Xilinx Webpack. I have asked the > local Xilinx FAE for help but he is not versed in VHDL. This can't be > as difficult as it seems... nobody would be using these devices. I am > getting the following signal for most all of the signals that I have > declared. I have patterned my code after one of the examples included > in WebPack(Xilinx software). > > WARNING:Xst:646 - Signal <dat_out<0>> is assigned but never used. > > I have included my code... it is not that large. > I would appreciate a kick in the right direction. > > Thanks, > David Thurlow > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > -- DESCRIPTION: > -- Decode/Respond to specific addressed commands > -- from the Host, via the BUS. > -- The commands control the FIFOs... READ/WRITE and > -- also send Status Bits back to the Host. > -- > -- > -- ************************************************************ > > entity decoder is > Port (ADDR : in std_logic_vector(9 downto 0); -- ADDRESS BUS > D : out std_logic_vector(5 downto 0); -- OUTPUT BITS 6 OF > THEM > N_GWR : in std_logic; -- BUS WRITE PULSE > N_GRD : in std_logic; -- BUS READ PULSE > N_DRV_ENAB: out std_logic; -- ENABLE THE 245 DRIVERS > PCK_READY: in std_logic; -- MESSAGE TO HOST READY > DIR : out std_logic; -- DIRECTION SEL FOR 245 DRIVERS > IN_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL > OUT_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL > N_RST_IN : out std_logic; -- RESET IN FIFOS > N_RST_OUT : out std_logic; -- RESET OUT FIFOS > N_RST_SYS : in std_logic; -- MASTER RESET > N_X_RD : out std_logic; -- HOST READS THE FIFOS > N_X_WR : out std_logic; -- HOST WRITES TO FIFOS > FIRST : out std_logic; -- SET BIT 9 IN FIFOa... 1st BYTE > LAST : out std_logic; -- SET BIT 9 IN FIFOb... last BYTE > G_BUS_ACTIVE : out std_logic; -- LIGHT LED DURING HOST CMDS > TRI_STATE : out std_logic; -- CONTROL GTS1...address selected > TRI_STATE_IN : in std_logic); -- CONTROL TRI-STATE OUTPUTS > end decoder; > > architecture Glonet_Decode of decoder is > -- the READx and WRITEx signals will be set when a proper > -- address and either /GRD or /GWR are active. They will be > -- cleared when /GRD or /GWR are inactive. > signal DAT_OUT : std_logic_vector(5 downto 0); -- STORE STATUS > FLAGS > signal READ0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND > /GRD > signal READ1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND > /GRD > signal WRITE0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND > /GWR > signal WRITE1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND > /GWR > signal WRITE2 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND > /GWR > signal WRITE3 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND > /GWR > begin > > process(N_GRD, N_GWR) -- THESE SIGNALS ARE THE TRIGGER FOR ANY > ACTION > > begin > -- IF A READ WAS COMMANDED, CHECK THE ADDRESS. > -- ONLY RESPOND TO SPECIFIC ADDRESSES. > -- SET 'FUNCTION' FLAG AND BUSY FLAG > if N_GRD'event and N_GRD = '0' THEN -- IF HOST READ AND NOT > BUSY > case ADDR is > when "0001110000" => -- IF 1C0h READ FIFOs > READ0 <= '1'; -- SET FUNCTION FLAG FOR USE LATER > when "0001110001" => -- IF 1C1h READ THE STATUS FLAG LATCH > READ1 <= '1'; -- SET FUNCTION FLAG > when others => -- READ PULSE NOT FOR US, IGNORE IT > end case; > END IF; > > if N_GWR'event and N_GWR = '0' THEN -- IF HOST WRITE AND NOT BUSY > case ADDR is > when "0001110000" => -- 1C0h WRITE TO FIFOs > WRITE0 <= '1'; > when "0001110001" => -- 1C1h WRITE TO FIFOs > WRITE1 <= '1'; > when "0001110010" => -- 1C2h WRITE TO FIFOs > WRITE2 <= '1'; > when "0001110011" => -- 1C3h RESET FIFOs > WRITE3 <= '1'; > when others => -- WRITE PULSE NOT FOR US, IGNORE IT > end case; > END IF; > > if N_GRD = '1' and N_GWR = '1' then -- NOTHING HAPPENING ON BUS > N_X_RD <= '1'; -- DISABLE IN_FIFO READS > N_DRV_ENAB <= '1'; -- DISABLE THE '245 DRIVERS > N_X_WR <= '1'; -- DISABLE OUT_FIFO WRITES > TRI_STATE <= '1'; -- TRI-STATE THE LATCHED BITS > FIRST <= '0'; -- RESET FLAG > LAST <= '0'; -- RESET FLAG > G_BUS_ACTIVE <= '1'; -- TURN OFF BUS ACTIVITY FLAG > END IF; > > if N_GRD = '1' then -- NO HOST READ PULSE > READ0 <= '0'; -- RESET BOTH FLAGS > READ1 <= '0'; > END IF; > > if N_GWR = '1' then -- NO HOST WRITE PULSE > WRITE0 <= '0'; -- RESET ALL WRITE FLAGS > WRITE1 <= '0'; > WRITE2 <= '0'; > WRITE3 <= '0'; > END IF; > END PROCESS; > > PROCESS(READ0,READ1,WRITE0,WRITE1,WRITE2,WRITE3,IN_FIFO_EMPTY, > OUT_FIFO_EMPTY) > begin > -- ********************************************************************** > -- FUNCTION FLAGS!!!! > -- ********************************************************************** > if READ0 = '1' then -- LET HOST READ FIFOs > DIR <= '1'; -- SET '245s TO SEND DIRECTION > N_X_RD <= '0'; -- HAVE THE FIFOs SPIT OUT A BYTE > N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS > G_BUS_ACTIVE <= '0'; -- TURN ON LED > END IF; > > if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS > DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS > DAT_OUT(1) <= IN_FIFO_EMPTY; > DAT_OUT(2) <= OUT_FIFO_EMPTY; > D <= DAT_OUT; > DIR <= '1'; -- SET '245s TO SEND DIRECTION > TRI_STATE <= '0'; -- ENABLE DATA TO OUTPUT LATCHES > N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS > G_BUS_ACTIVE <= '0'; -- TURN ON LED > END IF; > > if WRITE0 = '1' then -- HOST WRITES TO FIFOs > N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING > DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION > N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS > G_BUS_ACTIVE <= '0'; -- TURN ON LED > END IF; > > if WRITE1 = '1' then -- HOST WRITES TO FIFOs W/First FLAG > FIRST <= '1'; -- FLAG TO INDICATE FIRST BYTE OF MESSAGE > N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING > DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION > N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS > G_BUS_ACTIVE <= '0'; -- TURN ON LED > END IF; > > if WRITE2 = '1' then -- HOST WRITES TO FIFOs W/Last FLAG > LAST <= '1'; -- FLAG TO INDICATE LAST BYTE OF MESSAGE > N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING > DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION > N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS > G_BUS_ACTIVE <= '0'; -- TURN ON LED > END IF; > > if WRITE3 = '1' then -- HOST RESETS FIFOs ?? WE MAY NOT USE > THIS !! > G_BUS_ACTIVE <= '0'; -- TURN ON LED > END IF; > > END PROCESS; > > process(N_RST_SYS) > begin > -- ****************************************************************** > -- RESET: DEFAULT SETTINGS FOR DEVICE > -- ****************************************************************** > if N_RST_SYS = '0' then -- SYSTEM RESET > N_RST_IN <= '0'; -- RESET THE INPUT FIFOs > N_RST_OUT <= '0'; -- RESET THE OUTPUT FIFOs > N_DRV_ENAB <= '1'; -- DISABLE THE '245s > N_X_RD <= '1'; -- DISABLE THE FIFOs > N_X_WR <= '1'; -- > FIRST <= '0'; -- CLEAR FLAGS > LAST <= '0'; -- > G_BUS_ACTIVE <= '1'; -- SHUT OF LED > TRI_STATE <= '1'; -- TRISTATE OUTPUTS TO SHARED BUS > READ0 <= '0'; -- RESET ALL STATUS FLAGS > READ1 <= '0'; -- > WRITE0 <= '0'; -- > WRITE1 <= '0'; -- > WRITE2 <= '0'; -- > WRITE3 <= '0'; -- > DAT_OUT <= "000000"; -- RESET ALL FLAGS TO ZERO > ELSE > N_RST_IN <= '1'; -- FIFOs > N_RST_OUT <= '1'; -- > END IF; > END PROCESS; > end Glonet_Decode;
David T. wrote:

> I would appreciate a kick in the right direction.
> if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS > DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS What does DAT_OUT(0) get when READ1 /= '1' ? -- Mike Treseler
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3FF9E9AB.7020401@flukenetworks.com>...
> David T. wrote: > > > I would appreciate a kick in the right direction. > > > if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS > > DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS > > What does DAT_OUT(0) get when READ1 /= '1' ? > > -- Mike Treseler
I hoped it wouldn't matter... doesn't it retain the last state until it is given a new one?. Does it cause problems to leave this condition unattended?... I have to get used to the subtleties of VHDL. Thanks, David Thurlow