Hi experts,
my design is a rather simple demo for a spartan3E starter kit and uses
a picoblaze softcore and a grlib CAN2B core (can_mod).
I can't get it running...
I can read a good CR register value in reset mode (CR & A1 == 21 it is
a beginning...) but the other registers are not correct...
With my app, I get y N N N N...
I am a software guy, new to vhdl and design ... could someone
investigate my code ...
code and design is based on s3esk_startup.vhd (xilinx initial demo
shipped with kit)
regards,
vhdl
-=-=-=
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cantest is
Port ( led : out std_logic_vector(7 downto 0);
strataflash_oe : out std_logic;
strataflash_ce : out std_logic;
strataflash_we : out std_logic;
switch : in std_logic_vector(3 downto 0);
lcd_d : inout std_logic_vector(7 downto 4);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
clk : in std_logic;
rx_pin : in std_logic;
tx_pin : out std_logic
);
end cantest;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of cantest is
--
--gaisler grlib CAN2B
---------------------
component can_mod
generic ( memtech : integer );
port(
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic
);
end component;
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component control
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
proc_reset : out std_logic; --JTAG
Loader version
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
signal kcpsm3_reset : std_logic;
--
--
-- Signals for LCD operation
--
-- Tri-state output requires internal signals
-- 'lcd_drive' is used to differentiate between LCD and StrataFLASH
communications
-- which share the same data bits.
--
signal lcd_rw_control : std_logic;
signal lcd_output_data : std_logic_vector(7 downto 4);
signal lcd_drive : std_logic;
--
--
--signal for CAN2B
signal addr : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal can_cs : std_logic;
signal can_we : std_logic;
signal irq : std_logic;
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--StrataFLASH must be disabled to prevent it conflicting with the LCD
display
--
strataflash_oe <= '1';
strataflash_ce <= '1';
strataflash_we <= '1';
can: can_mod
generic map (memtech => 0) --generic ram
port map (
reset => kcpsm3_reset,
addr => addr,
data_in => data_in,
data_out => data_out,
cs => can_cs,
we => can_we,
clk => clk ,
rxi => rx_pin,
txo => tx_pin,
irq => irq);
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => kcpsm3_reset,
clk => clk);
control_rom: control
port map( address => address,
instruction => instruction,
proc_reset => kcpsm3_reset, --JTAG
Loader version
clk => clk);
-- The inputs connect via a pipelined multiplexer
--
input_ports: process(clk)
begin
if clk'event and clk='1' then
if read_strobe='1' then
case port_id(7 downto 6) is
--read switch data
when "00" =>
in_port <= "0000" & switch;
-- read LCD data at address 10xx xxxx
when "10" =>
in_port <= lcd_d & "0000";
-- read can data at address 11xx aaaa
when "11" =>
in_port <= data_out;
-- Don't care used for all other addresses to ensure minimum
logic implementation
when others => in_port <= "XXXXXXXX";
end case;
end if;
end if;
end process input_ports;
-- adding the output registers to the processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
case port_id(7 downto 6) is
-- Write to LEDs at address 80 hex.
when "10" =>
led <= out_port;
can_we <='0';
-- LCD data output and controls at address 40 hex.
when "01" =>
lcd_output_data <= out_port(7 downto 4);
lcd_drive <= out_port(3);
lcd_rs <= out_port(2);
lcd_rw_control <= out_port(1);
lcd_e <= out_port(0);
can_we <= '0';
-- CANB data
when "11" =>
can_we <= '1';
data_in <= out_port;
when others =>
can_we <= '0';
end case;
end if;
end if;
end process output_ports;
--can addr interface 32 registers
addr(7 downto 0) <= "00" & port_id(5 downto 0);
can_cs <= '1';
--
----------------------------------------------------------------------------------------------------------------------------------
-- LCD interface
----------------------------------------------------------------------------------------------------------------------------------
--
-- The 4-bit data port is bidirectional.
-- lcd_rw is '1' for read and '0' for write
-- lcd_drive is like a master enable signal which prevents either the
-- FPGA outputs or the LCD display driving the data lines.
--
--Control of read and write signal
lcd_rw <= lcd_rw_control and lcd_drive;
--use read/write control to enable output buffers.
lcd_d <= lcd_output_data when (lcd_rw_control='0' and lcd_drive='1')
else "ZZZZ";
end Behavioral;
control.psm
-=-=-=-=-=-=
;CAN2B registers
CONSTANT CR, C0
...
CONSTANT CDR, DF
;
CONSTANT LED_port, 80 ;8 simple LEDs
;
CONSTANT switch_port, 00 ;Read switches
and press buttons
;
;LCD interface ports
;
;The master enable signal is not used by the LCD
display itself
;but may be required to confirm that LCD
communication is active.
;This is required on the Spartan-3E Starter Kit if
the StrataFLASH
;is used because it shares the same data pins and
conflicts must be avoided.
;
CONSTANT LCD_output_port, 40 ;LCD character
module output data and control
...
CONSTANT ISR_preserve_s0, 01 ;Preserve s0
contents during ISR
CONSTANT count, 04
;
;
...
CONSTANT character_a, 61
...
CONSTANT character_BS, 08 ;Back Space
command character
;
;
;
;
;
;**************************************************************************************
;Initialise the system
;**************************************************************************************
;
cold_start: CALL LCD_reset ;initialise LCD
display
ENABLE INTERRUPT
;
load s0, 41
store s0, count
load s0,00
output s0, LED_port
;**************************************************************************************
;Main program
;**************************************************************************************
main_loop: LOAD s5, 10 ;Line 1 position 0
CALL LCD_cursor
CALL disp_msg
CALL delay_1s
LOAD s5, 20 ;Line 2 position 0
CALL LCD_cursor
call test_can1
jump main_loop
;*****************************
;END MAIN LOOP
;*****************************
test_can1: ;enter reset mode
load sa, 01
output sa, CR
wait: input sa,CR
and sa, 01
compare sa, 01
jump nz, wait
INPUT sa, CR
AND sa, A1
compare sa, 21
call Z, disp_ok
compare sa, 21
call NZ, disp_nok
INPUT sa, CMR
compare sa, FF
call Z, disp_ok
compare sa, FF
call NZ, disp_nok
INPUT sa, SR
compare sa, 0C
call Z, disp_ok
compare sa, 0C
call NZ, disp_nok
INPUT sa, IR
compare sa, E0
call Z, disp_ok
compare sa, E0
call NZ, disp_nok
INPUT sa, CDR
compare sa, 00
call Z, disp_ok
compare sa, 00
call NZ, disp_nok
RETURN
test_can2: ;nok...
load sa, 01
OUTPUT sa, CR
call delay_1ms
LOAD sa, 00
OUTPUT sa, CDR
LOAD sa, 81
OUTPUT sa, BTR0
LOAD sa, 25
OUTPUT s0, BTR1
LOAD sa, 15
OUTPUT s0, ACR
LOAD sa, 01
OUTPUT sa, AMR
load sa, 00
OUTPUT sa, CR
call delay_1ms
load sa,3E
OUTPUT sa, CR
LOAD sa, A3
OUTPUT s0, TXID1
LOAD sa, 83
OUTPUT sa, TXID2
LOAD sa, 11
OUTPUT sa, TX1
LOAD sa, 22
OUTPUT sa, TX2
LOAD sa, 33
OUTPUT s0, TX3
LOAD sa, 44
OUTPUT sa, TX4
send: LOAD sa, 01
OUTPUT sa, CMR
CALL delay_1ms
;jump send
RETURN
;**************************************************************************************
;LCD text messages
;**************************************************************************************
...
;
;
;
;
;**************************************************************************************
;Software delay routines
;**************************************************************************************
;
...
;**************************************************************************************
;LCD Character Module Routines
;**************************************************************************************
...
;**************************************************************************************
;Interrupt Vector
;**************************************************************************************
;
ADDRESS 3FF
JUMP ISR
;
;
PicoBlaze and (leon) grlib CAN2B core / spartan3E starter kit
Started by ●November 9, 2006
