MPMC2: MPMC2 with DDR2 SDRAM

Hi,

Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?

Thanks.

zyan schrieb:

> Hi,
>
> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
>
> Thanks.

same here :(
all attempts to get MPMC2 DDR2 designs to work have failed so far
have tested on custom V4 board with single 16bit device and on ML501
all attempts failing

I guess the only way to get going is to purchase a eval board that *IS*
supported by MPMC2 like ml410 and get it working there, and then
translate that working design to a custom board.

Antti

Antti wrote:
> zyan schrieb:
> 
>> Hi,
>>
>> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
>>
>> Thanks.
> 
> same here :(
> all attempts to get MPMC2 DDR2 designs to work have failed so far
> have tested on custom V4 board with single 16bit device and on ML501
> all attempts failing
> 
> I guess the only way to get going is to purchase a eval board that *IS*
> supported by MPMC2 like ml410 and get it working there, and then
> translate that working design to a custom board.
> 
> Antti
> 

Hi Antti,

MPMC2 works fine on ML410 DDR2. You might want to start with those 
settings and then customize for your project.

BTW, MPMC2 does not support Virtex5 as yet, so it will not work on ML501.

/Siva

It works on ML403 and ML405 boards. Sorry I don't have any specific
information on what to look at since I started from the reference
designs. Have you simulated your design?

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools/


zyan wrote:
> Hi,
>
> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
> 
> Thanks.

Siva Velusamy schrieb:

> Antti wrote:
> > zyan schrieb:
> >
> >> Hi,
> >>
> >> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
> >>
> >> Thanks.
> >
> > same here :(
> > all attempts to get MPMC2 DDR2 designs to work have failed so far
> > have tested on custom V4 board with single 16bit device and on ML501
> > all attempts failing
> >
> > I guess the only way to get going is to purchase a eval board that *IS*
> > supported by MPMC2 like ml410 and get it working there, and then
> > translate that working design to a custom board.
> >
> > Antti
> >
>
> Hi Antti,
>
> MPMC2 works fine on ML410 DDR2. You might want to start with those
> settings and then customize for your project.
>
> BTW, MPMC2 does not support Virtex5 as yet, so it will not work on ML501.
>
> /Siva

Hi Siva,

I belive that MPMC2 DDR2 works on "Xilinx provided boards" but the
question is how to make it to work on an "non Xilinx board?"

I have several custom V4 boards with DDR2 and I have ML501, I assumed
that as MPMC2 generates UCF file that matches ML501 so first step would
be to get MPMC2 to work on ML501 and then derive a new design for the
custom board. I dont have ML410 or any other "xilinx supported board"
for testing.

can you tell me why MPMC2 1.7 does not support V5? is it because
1) it is not tested (but may work) ?
2) IP core just want work for V-5 architecture
3) IP core is ok for V-5 but want work on ML501 because of clock buffer
errata in ES silicon as described in EN049.PDF ?

Are there any plans to make MPMC2 to support Virtex-5? If yes when can
we expect this?

Getting MPMC2 to work on our custom V4 DDR2 boards is really urgent, so
any help is welcome.

For now I will drop any MPMC2 testing on ML501 and try to modify some
MPMC2 archived project for our purpose, so far I did regenerate new
project (and that failed to workI)

Antti

I got it working on Virtex4FX12 MiniModule AKA GSRD2. Actually I had no
problems at all. But It has only 64MB DDR x16. I also tried running DDR
at 200MHz but it did not pass the memory test since it is only DDR333.
I also don't know where these MPMC2 guys got the datasheet for this RAM
to get the Fmax=200 at CL=3.
But I do have some problems writing to NPI in 64 word bursts and
premature ending.

BTW: There are so many parameters to adjust that there is a good chance
that the system does not work at all.

Cheers,

Guru



Antti wrote:
> Siva Velusamy schrieb:
>
> > Antti wrote:
> > > zyan schrieb:
> > >
> > >> Hi,
> > >>
> > >> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
> > >>
> > >> Thanks.
> > >
> > > same here :(
> > > all attempts to get MPMC2 DDR2 designs to work have failed so far
> > > have tested on custom V4 board with single 16bit device and on ML501
> > > all attempts failing
> > >
> > > I guess the only way to get going is to purchase a eval board that *IS*
> > > supported by MPMC2 like ml410 and get it working there, and then
> > > translate that working design to a custom board.
> > >
> > > Antti
> > >
> >
> > Hi Antti,
> >
> > MPMC2 works fine on ML410 DDR2. You might want to start with those
> > settings and then customize for your project.
> >
> > BTW, MPMC2 does not support Virtex5 as yet, so it will not work on ML501.
> >
> > /Siva
>
> Hi Siva,
>
> I belive that MPMC2 DDR2 works on "Xilinx provided boards" but the
> question is how to make it to work on an "non Xilinx board?"
>
> I have several custom V4 boards with DDR2 and I have ML501, I assumed
> that as MPMC2 generates UCF file that matches ML501 so first step would
> be to get MPMC2 to work on ML501 and then derive a new design for the
> custom board. I dont have ML410 or any other "xilinx supported board"
> for testing.
>
> can you tell me why MPMC2 1.7 does not support V5? is it because
> 1) it is not tested (but may work) ?
> 2) IP core just want work for V-5 architecture
> 3) IP core is ok for V-5 but want work on ML501 because of clock buffer
> errata in ES silicon as described in EN049.PDF ?
>
> Are there any plans to make MPMC2 to support Virtex-5? If yes when can
> we expect this?
>
> Getting MPMC2 to work on our custom V4 DDR2 boards is really urgent, so
> any help is welcome.
>
> For now I will drop any MPMC2 testing on ML501 and try to modify some
> MPMC2 archived project for our purpose, so far I did regenerate new
> project (and that failed to workI)
> 
> Antti

> I belive that MPMC2 DDR2 works on "Xilinx provided boards" but the
> question is how to make it to work on an "non Xilinx board?"
> 
> I have several custom V4 boards with DDR2 and I have ML501, I assumed
> that as MPMC2 generates UCF file that matches ML501 so first step would
> be to get MPMC2 to work on ML501 and then derive a new design for the
> custom board. I dont have ML410 or any other "xilinx supported board"
> for testing.
> 
> can you tell me why MPMC2 1.7 does not support V5? is it because
> 1) it is not tested (but may work) ?
> 2) IP core just want work for V-5 architecture
> 3) IP core is ok for V-5 but want work on ML501 because of clock buffer
> errata in ES silicon as described in EN049.PDF ?
> 
> Are there any plans to make MPMC2 to support Virtex-5? If yes when can
> we expect this?
> 
> Getting MPMC2 to work on our custom V4 DDR2 boards is really urgent, so
> any help is welcome.
> 
> For now I will drop any MPMC2 testing on ML501 and try to modify some
> MPMC2 archived project for our purpose, so far I did regenerate new
> project (and that failed to workI)
> 

Hi Antti -

Unfortunately I do not have good answers for any of the above questions. 
I do know that the next release of MPMC2 will support V5. I do not know 
the schedules.

/Siva

Antti wrote:

>>Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?

> 
> same here :(
> all attempts to get MPMC2 DDR2 designs to work have failed so far
> have tested on custom V4 board with single 16bit device and on ML501
> all attempts failing
> 

And same here (mch_opb_ddr2 not MPMC) - we've spent a week trying to get the
mch_opb_ddr2 core talking to a Micron 512Mb 32Mx16 -37E part on a PCIe board -
no luck.  The board is OK - there's a MIG design that works fine.

Webcase is in progress, we'll see what happens.

In the process of trying to simulate the design, I discovered that the standard
practice of chaining one DCM's "locked" pin to the next DCM's "reset" pin is not
supported by the simulation libraries - you must have at least three clock
cycles on CLKIN before releasing reset or the simulated DCM refuses to start.
Sigh..

John

That is the memory that I am using. Besides MPMC2, I tried plb_ddr2 also. Didn't work :(

I queried through the webcase and Xilinx said they only support their own product. As the Micron DDR2 is "external" to them. They do not provide support for that. Sigh!

-zyan

John Williams schrieb:

> Antti wrote:
>
> >>Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
>
> >
> > same here :(
> > all attempts to get MPMC2 DDR2 designs to work have failed so far
> > have tested on custom V4 board with single 16bit device and on ML501
> > all attempts failing
> >
>
> And same here (mch_opb_ddr2 not MPMC) - we've spent a week trying to get the
> mch_opb_ddr2 core talking to a Micron 512Mb 32Mx16 -37E part on a PCIe board -
> no luck.  The board is OK - there's a MIG design that works fine.
>
> Webcase is in progress, we'll see what happens.
>
> In the process of trying to simulate the design, I discovered that the standard
> practice of chaining one DCM's "locked" pin to the next DCM's "reset" pin is not
> supported by the simulation libraries - you must have at least three clock
> cycles on CLKIN before releasing reset or the simulated DCM refuses to start.
> Sigh..
>
> John

John,

the DDR2 issue gets more confusing:

OPB_MCH_DDR2 (EDK 8.2 SP2) worked for me like magic, just out of box,
all working, no issues
PLB_DDR2 works on ML501 (but uses patched EDK core), well Xilinx
reports that out of box PLB_DDR2 also works on ML501 (I have failed
with it)
there is customer report who got PLB_DDR2 working on custom board (but
after getting patch from Xilinx FAE)

MPMC2 has SERIOUS bug with the OPB interface, the datapath FIFO used
just doesnt work at all, everything stalls on first read, tested both
FPGA design and simulation

I am now trying MPMC2 core with PLB selected as port interface, I hope
this will work (I have problems at the moment with the OPB2PLB bridge
but those are possible minor mis-config)

For what my impressions are, is that DDR2 isnt so much harder than DDR
at all, at least when you have single chip (and not SODIMM), if you
happen to have config setup that is supported by the IP core

the MIG test is something you should not trust 100% I have seen patches
to MIG where in commentary it says, "ah this must be delayed by 2
clocks, or the error out will not work.."

so make sure the MIG test really is reporting errors, that is inject
errors and monitor the status

Antti