regarding changing serial data out to LVDS form

hi all,

i have serial data out in my design and i need to convert it to LVDS
signal how can i covert it to LVDS . my end system needs differential
data as input so i need to convert to LVDS. i have written code in vhdl
and data out is ready which is serial data . i am using spartan 3e
fpga.....

can any one please explain how to change to LVDS. 


regards 
srikanth

<ekavirsrikanth@gmail.com> wrote in message 
news:1163413947.064149.16520@f16g2000cwb.googlegroups.com...
>
>
> hi all,
>
> i have serial data out in my design and i need to convert it to LVDS
> signal how can i covert it to LVDS . my end system needs differential
> data as input so i need to convert to LVDS. i have written code in vhdl
> and data out is ready which is serial data . i am using spartan 3e
> fpga.....
>
> can any one please explain how to change to LVDS.
>
All voltage standards (like LVDS) are specified as user constraints. 
Consult the Spartan or ISE documentation for the precise details

KJ 

Give us a clue here.
Are you working in VHDL or Verilog?
Xilinx, Altera, or other?
Most systems that support LVDS have a technology dependent
component that will support LVDS transmissions. Unless we
know what you are working with, we can't help.

Brad Smallridge
aivision


<ekavirsrikanth@gmail.com> wrote in message 
news:1163413947.064149.16520@f16g2000cwb.googlegroups.com...
>
>
> hi all,
>
> i have serial data out in my design and i need to convert it to LVDS
> signal how can i covert it to LVDS . my end system needs differential
> data as input so i need to convert to LVDS. i have written code in vhdl
> and data out is ready which is serial data . i am using spartan 3e
> fpga.....
>
> can any one please explain how to change to LVDS.
>
>
> regards
> srikanth
> 

Oops. Belay that last message. I'm not reading well this
morning.

Here are some code snips from my Virtex4 platform which
should be about the same for your Spartan3s:

top level VHDL:

my_serial_to_cam2_OBUFDS : OBUFDS
port map (
 O  => cam2_serial_out_p,  -- to cam2
 OB => cam2_serial_out_n,  -- to cam2
 I  => serial_to_cam2 );

serial_from_cam2_IBUFDS : IBUFDS
port map (
 O  => serial_from_cam2,
 I  => cam2_serial_in_p,   -- from cam2
 IB => cam2_serial_in_n ); -- from cam2

Underneath the top level I have a code module that
deals with only non-differential signals. I never
did find out a way to simulate differential signals.

In your UCF file:

# Serial Port from and to CAM2
NET "cam2_serial_out_n" LOC = AF22; # HDR2_42
NET "cam2_serial_out_p" LOC = AF21; # HDR2_44
NET "cam2_serial_in_n"  LOC = AF20; # HDR2_30
NET "cam2_serial_in_p"  LOC = AF19; # HDR2_32
# differential termination applied to input IBUFD
INST serial_from_cam2_IBUFDS DIFF_TERM = TRUE; # must match top

Hope this helps.

Brad Smallridge
aivision






<ekavirsrikanth@gmail.com> wrote in message 
news:1163413947.064149.16520@f16g2000cwb.googlegroups.com...
>
>
> hi all,
>
> i have serial data out in my design and i need to convert it to LVDS
> signal how can i covert it to LVDS . my end system needs differential
> data as input so i need to convert to LVDS. i have written code in vhdl
> and data out is ready which is serial data . i am using spartan 3e
> fpga.....
>
> can any one please explain how to change to LVDS.
>
>
> regards
> srikanth
> 

And another oops.
INST my_serial_from_cam2_IBUFDS DIFF_TERM = TRUE; # must match top
Brad