I am new to CPLD's and I am trying to make a new design incorporating some of the old abel code. I am using schematic entry (XC9572). I have converted the abel code into symbols and incorporating them to my schematic. In the new design I am not using many of the input and outputs that were defined in the abel code but I dont want to fiddle with that and so I am using the code as it is. Now when I synthesize I get following warnings.. WARNING:Xst:647 - Input <A00> is never used. WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a combinatorial loop: _xor0004, BEL, _xor0002 WARNING:Xst:1354 - Port SPAREI is not connected, attached property removed (LOC) Should I worry about these warnings because I am not using all these ports/signals/input? At present I have connected all unused inputs to ground and left the unused outputs as it is. Is that the right approach? Thanks for any responses...
Warnings in Xilinx 8.2i
Started by ●November 16, 2006
Reply by ●November 16, 20062006-11-16
learnfpga wrote:> I am new to CPLD's and I am trying to make a new design incorporating > some of the old abel code. I am using schematic entry (XC9572). I have > converted the abel code into symbols and incorporating them to my > schematic. In the new design I am not using many of the input and > outputs that were defined in the abel code but I dont want to fiddle > with that and so I am using the code as it is. > > Now when I synthesize I get following warnings.. > > WARNING:Xst:647 - Input <A00> is never used. > > WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. > > WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a > combinatorial loop: _xor0004, BEL, _xor0002 > > WARNING:Xst:1354 - Port SPAREI is not connected, attached property > removed (LOC) > > > Should I worry about these warnings because I am not using all these > ports/signals/input? > > At present I have connected all unused inputs to ground and left the > unused outputs as it is. Is that the right approach? > > Thanks for any responses...Check the fitter report files, they will show you what _actually_ happened. Why design in schematic, if you already have the code in abel ?. AFAIK Xilinx still supports that flow fine for CPLDs. -jg
Reply by ●November 17, 20062006-11-17
Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag news:455cf081$1@clear.net.nz...> learnfpga wrote: >> I am new to CPLD's and I am trying to make a new design incorporating >> some of the old abel code. I am using schematic entry (XC9572). I have >> converted the abel code into symbols and incorporating them to my >> schematic. In the new design I am not using many of the input and >> outputs that were defined in the abel code but I dont want to fiddle >> with that and so I am using the code as it is. >> >> Now when I synthesize I get following warnings.. >> >> WARNING:Xst:647 - Input <A00> is never used. >> >> WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. >> >> WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a >> combinatorial loop: _xor0004, BEL, _xor0002 >> >> WARNING:Xst:1354 - Port SPAREI is not connected, attached property >> removed (LOC) >> >> >> Should I worry about these warnings because I am not using all these >> ports/signals/input? >> >> At present I have connected all unused inputs to ground and left the >> unused outputs as it is. Is that the right approach? >> >> Thanks for any responses... > > Check the fitter report files, they will show you what _actually_ > happened. > > Why design in schematic, if you already have the code in abel ?. > AFAIK Xilinx still supports that flow fine for CPLDs. > > -jg >Jim this is a bug in ISE 8.x it only happens for 95xx CPLDs IMHO the only solution is to use ISE 7.1 or 6.3 for XC95xx Antti
Reply by ●November 17, 20062006-11-17
Antti Lukats wrote:> Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag > news:455cf081$1@clear.net.nz... > > learnfpga wrote: > >> I am new to CPLD's and I am trying to make a new design incorporating > >> some of the old abel code. I am using schematic entry (XC9572). I have > >> converted the abel code into symbols and incorporating them to my > >> schematic. In the new design I am not using many of the input and > >> outputs that were defined in the abel code but I dont want to fiddle > >> with that and so I am using the code as it is. > >> > >> Now when I synthesize I get following warnings.. > >> > >> WARNING:Xst:647 - Input <A00> is never used. > >> > >> WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. > >> > >> WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a > >> combinatorial loop: _xor0004, BEL, _xor0002 > >> > >> WARNING:Xst:1354 - Port SPAREI is not connected, attached property > >> removed (LOC) > >> > >> > >> Should I worry about these warnings because I am not using all these > >> ports/signals/input? > >> > >> At present I have connected all unused inputs to ground and left the > >> unused outputs as it is. Is that the right approach? > >> > >> Thanks for any responses... > > > > Check the fitter report files, they will show you what _actually_ > > happened. > > > > Why design in schematic, if you already have the code in abel ?. > > AFAIK Xilinx still supports that flow fine for CPLDs.Thanks for the response.... Because of the time constraint involved I am most comfortable with schematic instead of abel.> > > > -jg > > > > Jim > > this is a bug in ISE 8.x it only happens for 95xx CPLDs > IMHO the only solution is to use ISE 7.1 or 6.3 for XC95xx >I changed the CPLD to xc2c128 and XCR3128XL. I still got the same warnings as before.... Should I try using ISE7.1? Thanks> Antti
Reply by ●November 17, 20062006-11-17
learnfpga schrieb:> Antti Lukats wrote: > > Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag > > news:455cf081$1@clear.net.nz... > > > learnfpga wrote: > > >> I am new to CPLD's and I am trying to make a new design incorporating > > >> some of the old abel code. I am using schematic entry (XC9572). I have > > >> converted the abel code into symbols and incorporating them to my > > >> schematic. In the new design I am not using many of the input and > > >> outputs that were defined in the abel code but I dont want to fiddle > > >> with that and so I am using the code as it is. > > >> > > >> Now when I synthesize I get following warnings.. > > >> > > >> WARNING:Xst:647 - Input <A00> is never used. > > >> > > >> WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. > > >> > > >> WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a > > >> combinatorial loop: _xor0004, BEL, _xor0002 > > >> > > >> WARNING:Xst:1354 - Port SPAREI is not connected, attached property > > >> removed (LOC) > > >> > > >> > > >> Should I worry about these warnings because I am not using all these > > >> ports/signals/input? > > >> > > >> At present I have connected all unused inputs to ground and left the > > >> unused outputs as it is. Is that the right approach? > > >> > > >> Thanks for any responses... > > > > > > Check the fitter report files, they will show you what _actually_ > > > happened. > > > > > > Why design in schematic, if you already have the code in abel ?. > > > AFAIK Xilinx still supports that flow fine for CPLDs. > > Thanks for the response.... > Because of the time constraint involved I am most comfortable with > schematic instead of abel. > > > > > > > -jg > > > > > > > Jim > > > > this is a bug in ISE 8.x it only happens for 95xx CPLDs > > IMHO the only solution is to use ISE 7.1 or 6.3 for XC95xx > > > > I changed the CPLD to xc2c128 and XCR3128XL. I still got the same > warnings as before.... > > Should I try using ISE7.1? Thankswell what I witnessed was single design 8.1 or 8.2 95xx target several input pins are 'left out' coolrunner/II or any FPGA target ALL OK 6.3 or 7.1 95xx all input pins remained ok so I assumed that only 95xx fitter has been broken in 8.x but maybe its even more global mess with 8.x CPLDs try 7.1 and open an webcase also Antti
Reply by ●November 17, 20062006-11-17
Some of these warnings can be ignored, but some are potentially signficant problems. Unused inputs can be safely ignored. Assigned, but not used can be ignored if you are sure this is a signal that you intended to not use. A combinatorial loop may be an error or it may be intentional, but outside the normal usage of these devices. A combinatorial loop can be an intended latch or an unintended latch. You need to figure out which you have. The bottom line is that you should design to avoid warnings because otherwise you need to investigate each one to make sure it is not a real problem. By leaving them in you need to at least go through the list each time to make sure no new ones have been generated. learnfpga wrote:> I am new to CPLD's and I am trying to make a new design incorporating > some of the old abel code. I am using schematic entry (XC9572). I have > converted the abel code into symbols and incorporating them to my > schematic. In the new design I am not using many of the input and > outputs that were defined in the abel code but I dont want to fiddle > with that and so I am using the code as it is. > > Now when I synthesize I get following warnings.. > > WARNING:Xst:647 - Input <A00> is never used. > > WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. > > WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a > combinatorial loop: _xor0004, BEL, _xor0002 > > WARNING:Xst:1354 - Port SPAREI is not connected, attached property > removed (LOC) > > > Should I worry about these warnings because I am not using all these > ports/signals/input? > > At present I have connected all unused inputs to ground and left the > unused outputs as it is. Is that the right approach? > > Thanks for any responses...
Reply by ●November 17, 20062006-11-17
rickman schrieb:> Some of these warnings can be ignored, but some are potentially > signficant problems. > > Unused inputs can be safely ignored. Assigned, but not used can be > ignored if you are sure this is a signal that you intended to not use. > A combinatorial loop may be an error or it may be intentional, but > outside the normal usage of these devices. A combinatorial loop can be > an intended latch or an unintended latch. You need to figure out which > you have. > > The bottom line is that you should design to avoid warnings because > otherwise you need to investigate each one to make sure it is not a > real problem. By leaving them in you need to at least go through the > list each time to make sure no new ones have been generated. > > > learnfpga wrote: > > I am new to CPLD's and I am trying to make a new design incorporating > > some of the old abel code. I am using schematic entry (XC9572). I have > > converted the abel code into symbols and incorporating them to my > > schematic. In the new design I am not using many of the input and > > outputs that were defined in the abel code but I dont want to fiddle > > with that and so I am using the code as it is. > > > > Now when I synthesize I get following warnings.. > > > > WARNING:Xst:647 - Input <A00> is never used. > > > > WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. > > > > WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a > > combinatorial loop: _xor0004, BEL, _xor0002 > > > > WARNING:Xst:1354 - Port SPAREI is not connected, attached property > > removed (LOC) > > > > > > Should I worry about these warnings because I am not using all these > > ports/signals/input? > > > > At present I have connected all unused inputs to ground and left the > > unused outputs as it is. Is that the right approach? > > > > Thanks for any responses...hi rickman, maybe it is 2 different issues. in my case some inputs that are REALLY used are not present when targetting XC95xx using 8.1 or 8.2 and are present in all other tested target device and ISE version combinations. Antti
Reply by ●November 17, 20062006-11-17
Antti wrote:> rickman schrieb: > > > Some of these warnings can be ignored, but some are potentially > > signficant problems. > > > > Unused inputs can be safely ignored. Assigned, but not used can be > > ignored if you are sure this is a signal that you intended to not use. > > A combinatorial loop may be an error or it may be intentional, but > > outside the normal usage of these devices. A combinatorial loop can be > > an intended latch or an unintended latch. You need to figure out which > > you have. > > > > The bottom line is that you should design to avoid warnings because > > otherwise you need to investigate each one to make sure it is not a > > real problem. By leaving them in you need to at least go through the > > list each time to make sure no new ones have been generated. > > > > > > learnfpga wrote: > > > I am new to CPLD's and I am trying to make a new design incorporating > > > some of the old abel code. I am using schematic entry (XC9572). I have > > > converted the abel code into symbols and incorporating them to my > > > schematic. In the new design I am not using many of the input and > > > outputs that were defined in the abel code but I dont want to fiddle > > > with that and so I am using the code as it is. > > > > > > Now when I synthesize I get following warnings.. > > > > > > WARNING:Xst:647 - Input <A00> is never used. > > > > > > WARNING:Xst:646 - Signal <CARRY_12> is assigned but never used. > > > > > > WARNING:Xst:2170 - Unit PN67c : the following signal(s) form a > > > combinatorial loop: _xor0004, BEL, _xor0002 > > > > > > WARNING:Xst:1354 - Port SPAREI is not connected, attached property > > > removed (LOC) > > > > > > > > > Should I worry about these warnings because I am not using all these > > > ports/signals/input? > > > > > > At present I have connected all unused inputs to ground and left the > > > unused outputs as it is. Is that the right approach? > > > > > > Thanks for any responses... > > hi rickman, > > maybe it is 2 different issues. > > in my case some inputs that are REALLY used are not present > when targetting XC95xx using 8.1 or 8.2 and are present in all > other tested target device and ISE version combinations.I'm not sure what you mean by that. But the bottom line is you need to trace each of the warnings back to the root cause and figure out if it a "real" problem or not. Or you can just fix the warning by connecting your "unused" inputs to something such as an unused output? Like I said, the warning about combinatorial logic loop is not an input issue, you have a potential latch either by intent or unintentional. You need to figure out if that one is a real error or not.
Reply by ●November 17, 20062006-11-17
rickman schrieb:> Antti wrote: > > rickman schrieb: > > > > in my case some inputs that are REALLY used are not present > > when targetting XC95xx using 8.1 or 8.2 and are present in all > > other tested target device and ISE version combinations. > > I'm not sure what you mean by that. But the bottom line is you need to > trace each of the warnings back to the root cause and figure out if it > a "real" problem or not. Or you can just fix the warning by connecting > your "unused" inputs to something such as an unused output? > > Like I said, the warning about combinatorial logic loop is not an input > issue, you have a potential latch either by intent or unintentional. > You need to figure out if that one is a real error or not.rick, in my case the inputs reported as unused are used for sure !!! they are connected by design, and no chance they got optimized away _unless_ the tools _mess_up_, they are used and reported as used in ** ALL ** cases except the combination of: XC95xx and ISE 8.x 100% the same design yields to reports with no warning and proper pin useage. there is nothing to trace the issue, it goes away if I use ISE prior to 8.x or any other device except 95xx Antti
Reply by ●November 17, 20062006-11-17
Antti wrote:> rickman schrieb: > > > Antti wrote: > > > rickman schrieb: > > > > > > in my case some inputs that are REALLY used are not present > > > when targetting XC95xx using 8.1 or 8.2 and are present in all > > > other tested target device and ISE version combinations. > > > > I'm not sure what you mean by that. But the bottom line is you need to > > trace each of the warnings back to the root cause and figure out if it > > a "real" problem or not. Or you can just fix the warning by connecting > > your "unused" inputs to something such as an unused output? > > > > Like I said, the warning about combinatorial logic loop is not an input > > issue, you have a potential latch either by intent or unintentional. > > You need to figure out if that one is a real error or not. > > rick, > > in my case the inputs reported as unused are used for sure !!! > they are connected by design, and no chance they got optimized away > _unless_ the tools _mess_up_, they are used and reported as used in ** > ALL ** cases except the combination of: > > XC95xx and ISE 8.x > > 100% the same design yields to reports with no warning and proper pin > useage. > > there is nothing to trace the issue, it goes away if I use ISE prior to > 8.x or any other device except 95xxI got you mixed up with the OP.
