combinatorical divide by 2 in FPGA

Hi

this may sound strange but I need flip flop or divide by 2 element that
is made purely out of combinatorical logic and passes fpga
implementation without being optimized away, and work in FPGA fabric. I
tried some D-flop code but it gets really optimized away and doesnt
work.

I wonder if someone has a solution for this. It really must be pure
logic, eg using DCM or BUFR is not ok, the solution must not use any
fabric flip flops or fabric clocked primitives at all.

Antti

Antti wrote:

> Hi
> 
> this may sound strange but I need flip flop or divide by 2 element that
> is made purely out of combinatorical logic and passes fpga
> implementation without being optimized away, and work in FPGA fabric. I
> tried some D-flop code but it gets really optimized away and doesnt
> work.
> 
> I wonder if someone has a solution for this. It really must be pure
> logic, eg using DCM or BUFR is not ok, the solution must not use any
> fabric flip flops or fabric clocked primitives at all.

Hi Antti,
  One has to wonder .. why ? :)

  You will have to fight/override the tools, as this is not-natural as 
far as they are concerned.
  I tried this a while ago - in my case, a latch in PLD foldback nodes, 
and the logic itself is not complex, but the tools take one look at
the buried hold loops, and optimize them away !
  -jg

Jim Granville schrieb:

> Antti wrote:
>
> > Hi
> >
> > this may sound strange but I need flip flop or divide by 2 element that
> > is made purely out of combinatorical logic and passes fpga
> > implementation without being optimized away, and work in FPGA fabric. I
> > tried some D-flop code but it gets really optimized away and doesnt
> > work.
> >
> > I wonder if someone has a solution for this. It really must be pure
> > logic, eg using DCM or BUFR is not ok, the solution must not use any
> > fabric flip flops or fabric clocked primitives at all.
>
> Hi Antti,
>   One has to wonder .. why ? :)
>
>   You will have to fight/override the tools, as this is not-natural as
> far as they are concerned.
>   I tried this a while ago - in my case, a latch in PLD foldback nodes,
> and the logic itself is not complex, but the tools take one look at
> the buried hold loops, and optimize them away !
>   -jg

why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA
configuration is completed, eg at the time when fabric clocked
resources are not useable.

and yes it seems like kinda PITA thing todo.

Antti

Antti <Antti.Lukats@xilant.com> wrote:
> Jim Granville schrieb:

> > Antti wrote:
> >
> > > Hi
> > >
> > > this may sound strange but I need flip flop or divide by 2 element that
> > > is made purely out of combinatorical logic and passes fpga
> > > implementation without being optimized away, and work in FPGA fabric. I
> > > tried some D-flop code but it gets really optimized away and doesnt
> > > work.
> > >
> > > I wonder if someone has a solution for this. It really must be pure
> > > logic, eg using DCM or BUFR is not ok, the solution must not use any
> > > fabric flip flops or fabric clocked primitives at all.
> >
> > Hi Antti,
> >   One has to wonder .. why ? :)
> >
> >   You will have to fight/override the tools, as this is not-natural as
> > far as they are concerned.
> >   I tried this a while ago - in my case, a latch in PLD foldback nodes,
> > and the logic itself is not complex, but the tools take one look at
> > the buried hold loops, and optimize them away !
> >   -jg

> why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA
> configuration is completed, eg at the time when fabric clocked
> resources are not useable.

> and yes it seems like kinda PITA thing todo.

Can't you delay startup of the rest of the circuit while starting the divider
immediately after configuartion?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Uwe Bonnes schrieb:

> Antti <Antti.Lukats@xilant.com> wrote:
> > Jim Granville schrieb:
>
> > > Antti wrote:
> > >
> > > > Hi
> > > >
> > > > this may sound strange but I need flip flop or divide by 2 element that
> > > > is made purely out of combinatorical logic and passes fpga
> > > > implementation without being optimized away, and work in FPGA fabric. I
> > > > tried some D-flop code but it gets really optimized away and doesnt
> > > > work.
> > > >
> > > > I wonder if someone has a solution for this. It really must be pure
> > > > logic, eg using DCM or BUFR is not ok, the solution must not use any
> > > > fabric flip flops or fabric clocked primitives at all.
> > >
> > > Hi Antti,
> > >   One has to wonder .. why ? :)
> > >
> > >   You will have to fight/override the tools, as this is not-natural as
> > > far as they are concerned.
> > >   I tried this a while ago - in my case, a latch in PLD foldback nodes,
> > > and the logic itself is not complex, but the tools take one look at
> > > the buried hold loops, and optimize them away !
> > >   -jg
>
> > why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA
> > configuration is completed, eg at the time when fabric clocked
> > resources are not useable.
>
> > and yes it seems like kinda PITA thing todo.
>
> Can't you delay startup of the rest of the circuit while starting the divider
> immediately after configuartion?
>
> --
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I want to quick start the STARTUP primitive without the use of external
clocks. so I need 10 pulses at the time when GSR GTS are asserted and
GWE is not released. this is maybe just a few config clokc pulses
*BEFORE* the FPGA actually starts to work. only wiring and
combinatorical logic is activated. the divider is only need *until*
done goes high, not any more after that.

Antti

"Antti" <Antti.Lukats@xilant.com> wrote in message 
news:1163754102.129370.31240@k70g2000cwa.googlegroups.com...
> Hi
>
> this may sound strange but I need flip flop or divide by 2 element that
> is made purely out of combinatorical logic and passes fpga
> implementation without being optimized away, and work in FPGA fabric. I
> tried some D-flop code but it gets really optimized away and doesnt
> work.
>
> I wonder if someone has a solution for this. It really must be pure
> logic, eg using DCM or BUFR is not ok, the solution must not use any
> fabric flip flops or fabric clocked primitives at all.
>
> Antti
>
Hi Antti,
A while back I did something similar by instantiating LUT primitives.
e.g.:-

component LUT4
generic (
INIT : bit_vector := X"0000");
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC);
end component;

The tools weren't clever enough to look at the INIT number and attempt 
'optimisation'.
Good luck, Syms.

Antti wrote:
> Hi
> 
> this may sound strange but I need flip flop or divide by 2 element that
> is made purely out of combinatorical logic and passes fpga
> implementation without being optimized away, and work in FPGA fabric. I
> tried some D-flop code but it gets really optimized away and doesnt
> work.
> 
> I wonder if someone has a solution for this. It really must be pure
> logic, eg using DCM or BUFR is not ok, the solution must not use any
> fabric flip flops or fabric clocked primitives at all.
> 
> Antti

Sounds like you need a master/slave pair of latches (a DFF made out of 
gates).  The only trouble would be convincing the tool to not optimize 
out or complain too harshly about the combinatorial loops.

Two SR Latches chained together.  The S and R inputs are the normal and 
inverted signal from the other stage (inverted between one pair) and the 
clock acts as a 3rd input - normal on one SR Latch, inverted on the 
other - to each NAND gate to make the latch transparent or to allow the 
latch.

I'm thinking back to the old TI data book that mapped out all the simple 
TTL logic.  Since you don't need asynchronous set/reset logic, you 
should need just the 4 LUTs.

Antti wrote...
> Hi
>
> this may sound strange but I need flip flop or divide by 2 element that
> is made purely out of combinatorical logic and passes fpga
> implementation without being optimized away, and work in FPGA fabric. I
> tried some D-flop code but it gets really optimized away and doesnt
> work.
>
> I wonder if someone has a solution for this. It really must be pure
> logic, eg using DCM or BUFR is not ok, the solution must not use any
> fabric flip flops or fabric clocked primitives at all.

LUT instantiation. But you already know that. A good excuse to revisit those
Digital Logic 101 textbooks...

My memory is that Peter Alfke did this a while back, possibly in his search
for the fastest frequency counter in the galaxy ;-) Check the archives.

Tim schrieb:

> Antti wrote...
> > Hi
> >
> > this may sound strange but I need flip flop or divide by 2 element that
> > is made purely out of combinatorical logic and passes fpga
> > implementation without being optimized away, and work in FPGA fabric. I
> > tried some D-flop code but it gets really optimized away and doesnt
> > work.
> >
> > I wonder if someone has a solution for this. It really must be pure
> > logic, eg using DCM or BUFR is not ok, the solution must not use any
> > fabric flip flops or fabric clocked primitives at all.
>
> LUT instantiation. But you already know that. A good excuse to revisit those
> Digital Logic 101 textbooks...
>
> My memory is that Peter Alfke did this a while back, possibly in his search
> for the fastest frequency counter in the galaxy ;-) Check the archives.

yeah, I know the LUT path, will have todo it that way

Antti

John_H wrote:
> Antti wrote:
> > Hi
> >
> > this may sound strange but I need flip flop or divide by 2 element that
> > is made purely out of combinatorical logic and passes fpga
> > implementation without being optimized away, and work in FPGA fabric. I
> > tried some D-flop code but it gets really optimized away and doesnt
> > work.
> >
> > I wonder if someone has a solution for this. It really must be pure
> > logic, eg using DCM or BUFR is not ok, the solution must not use any
> > fabric flip flops or fabric clocked primitives at all.
> >
> > Antti
>
> Sounds like you need a master/slave pair of latches (a DFF made out of
> gates).  The only trouble would be convincing the tool to not optimize
> out or complain too harshly about the combinatorial loops.
>
> Two SR Latches chained together.  The S and R inputs are the normal and
> inverted signal from the other stage (inverted between one pair) and the
> clock acts as a 3rd input - normal on one SR Latch, inverted on the
> other - to each NAND gate to make the latch transparent or to allow the
> latch.
>
> I'm thinking back to the old TI data book that mapped out all the simple
> TTL logic.  Since you don't need asynchronous set/reset logic, you
> should need just the 4 LUTs.

Two LUTS/FF. Only one LUT required per latch, one for master latch, one
for slave, and . wiring, err routing, delays should be verified.
I'd list the init values, but haven't had my coffee yet this morning.
Just John