Hi, Altera is promoting its own soft-core processor, but it seems that they have "forgotten" the one of the most important things out of their tool-flow, namly it seems to impossible to merge the FPGA tool generated files after the flow with memory init files, like it doable with Xilinx and Lattice FPGA's. I just cant belive it, its one of the most useful things for the FPGA SoC designs, and its just not there? I really doesnt have time or fun to reverse engineer the .SOF format only to be able write the data2sof utility for Altera. Antti PS I am almost impressed about the Quality of Quartus 6.0, it took over 2 hours before it trapped into internal error and self terminated. For ISE 8.2 this time was 20 minutes, so Altera is leading as of software tool quality. Hm, nops, I dont recall Lattice tools to have self termination effects.
memory init in Altera bitfiles, (like data2mem) is it possible?
Started by ●November 17, 2006
Reply by ●November 17, 20062006-11-17
Hi,> I just cant belive it, its one of the most useful things for the FPGA > SoC designs, and its just not there? I really doesnt have time or fun > to reverse engineer the .SOF format only to be able write the data2sof > utility for Altera.I do, which chip do you intend to use ? the sof is really easy to parse, it's a sequence of option number / option length / option data: typedef struct _bitstream_option { uint16_t option; /* le */ uint32_t length; /* le */ char data[]; } PACKED bitstream_option_t; The RAM data is the option code 19, IIRC. The only hard part is figuring how to generate the CRC (option 8, seems like a CRC32, but...). JB
Reply by ●November 17, 20062006-11-17
Hi Antti,
Not sure if this helps but I use Altera's altsyncram memories in my design
which I pre-load using some generics
init_file => "..\cpu8088\nios_board\bootloader\mon86.hex"
then when the design is loaded I can change the memory contents on the fly
using the Quartus "In-System Memory contents editor". You do need to set
some more generics in advance to make this work:
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=RA86",
Regards,
Hans
www.ht-lab.com
"Antti" <Antti.Lukats@xilant.com> wrote in message
news:1163775000.686739.11560@h48g2000cwc.googlegroups.com...
> Hi,
>
> Altera is promoting its own soft-core processor, but it seems that they
> have "forgotten" the one of the most important things out of their
> tool-flow, namly it seems to impossible to merge the FPGA tool
> generated files after the flow with memory init files, like it doable
> with Xilinx and Lattice FPGA's.
>
> I just cant belive it, its one of the most useful things for the FPGA
> SoC designs, and its just not there? I really doesnt have time or fun
> to reverse engineer the .SOF format only to be able write the data2sof
> utility for Altera.
>
> Antti
> PS I am almost impressed about the Quality of Quartus 6.0, it took over
> 2 hours before it trapped into internal error and self terminated. For
> ISE 8.2 this time was 20 minutes, so Altera is leading as of software
> tool quality. Hm, nops, I dont recall Lattice tools to have self
> termination effects.
>
Reply by ●November 17, 20062006-11-17
jbnote schrieb:> Hi, > > > I just cant belive it, its one of the most useful things for the FPGA > > SoC designs, and its just not there? I really doesnt have time or fun > > to reverse engineer the .SOF format only to be able write the data2sof > > utility for Altera. > > I do, which chip do you intend to use ? > > the sof is really easy to parse, it's a sequence of option number / > option length / option data: > > typedef struct _bitstream_option { > uint16_t option; /* le */ > uint32_t length; /* le */ > char data[]; > } PACKED bitstream_option_t; > > The RAM data is the option code 19, IIRC. The only hard part is > figuring how to generate the CRC (option 8, seems like a CRC32, > but...). > > JBthanks JB well the ram data is 21 and the CRC is 16 bits, but otherwise it looks like doable to task to reverse the format Antti
Reply by ●November 17, 20062006-11-17
On Nov 17, 6:50 am, "Antti" <Antti.Luk...@xilant.com> wrote:> I just cant belive it, its one of the most useful things for the FPGA > SoC designs, and its just not there? I really doesnt have time or fun > to reverse engineer the .SOF format only to be able write the data2sof > utility for Altera.Antti, Others have commented on the general-purpose case, but since you made a specfiic reference to processors its worth discussing the soft-CPU flow for placing your code/data into onchip ram. No, this wasn't forgotten. In fact, support for doing this has been around about as long as Nios I/Nios II have been (6+ years now?). There are even several ways to accomplish the task: - If you are building your Nios II software in the IDE, it will take any coce/data linked into an onchip memory peripheral and use the elf2hex command to create a hex initialization file. The onchip RAM RTL generated by SOPC Builder is written out to be initialized this way; if you compile your design w/o any software having been built, memory will be left un-initialized, while if you first compile your software and then (re)compile in quartus, the .hex file(s) are used to initialize the memories. If you turn on verbose command line output from the IDE (window -> preferences -> nios II), you'll see the precise commands fly by on the console for future reference and command- line use. - Although the IDE-based flow doesn't do this now, you can even update your .sof file very quickly with onchip ram contents without risk of triggering an entire re-compile. I cannot recall the exact syntax of the command but I believe the compilation step is the Quartus Assembler (quartus_asm) - The "small" example design that ships with Nios II uses the above IDE-based method to initialize onchip RAM and as I recall the design's readme and other literature discuss this. Note that there are exclusions to what I've said, specifically for the types of onchip ram (m-ram blocks in Stratix, Stratix II) that cannot be initialized until runtime. The wizard to create an onchip ram in SOPC Builder allows you to choose which type of ram block will be used, if you desire, to ensure that you can pre-initialize contents if that is what you need to do. Jesse Kempa Altera Corp. jkempa --at-- altera --dot-- com
Reply by ●November 17, 20062006-11-17
kem...@yahoo.com schrieb:> On Nov 17, 6:50 am, "Antti" <Antti.Luk...@xilant.com> wrote: > > I just cant belive it, its one of the most useful things for the FPGA > > SoC designs, and its just not there? I really doesnt have time or fun > > to reverse engineer the .SOF format only to be able write the data2sof > > utility for Altera. > > Antti, > > Others have commented on the general-purpose case, but since you made a > specfiic reference to processors its worth discussing the soft-CPU flow > for placing your code/data into onchip ram. > > No, this wasn't forgotten. In fact, support for doing this has been > around about as long as Nios I/Nios II have been (6+ years now?). There are even > several ways to accomplish the task: > > - If you are building your Nios II software in the IDE, it will take > any coce/data linked into > an onchip memory peripheral and use the elf2hex command to create a hex > initialization > file. The onchip RAM RTL generated by SOPC Builder is written out to be > initialized this > way; if you compile your design w/o any software having been built, > memory will be left > un-initialized, while if you first compile your software and then > (re)compile in quartus, > the .hex file(s) are used to initialize the memories. > > If you turn on verbose command line output from the IDE (window -> > preferences -> nios II), > you'll see the precise commands fly by on the console for future > reference and command- > line use. > > - Although the IDE-based flow doesn't do this now, you can even update > your .sof > file very quickly with onchip ram contents without risk of triggering > an entire > re-compile. I cannot recall the exact syntax of the command but I > believe the compilation > step is the Quartus Assembler (quartus_asm) > > - The "small" example design that ships with Nios II uses the above > IDE-based > method to initialize onchip RAM and as I recall the design's readme and > other > literature discuss this. > > Note that there are exclusions to what I've said, specifically for the > types of > onchip ram (m-ram blocks in Stratix, Stratix II) that cannot be > initialized until > runtime. The wizard to create an onchip ram in SOPC Builder allows you > to > choose which type of ram block will be used, if you desire, to ensure > that you > can pre-initialize contents if that is what you need to do. > > Jesse Kempa > Altera Corp. > jkempa --at-- altera --dot-- comDear Jesse, I know about all you said above. but you missed the point. in Xilinx flow you can run a tool like: data2mem system.bit software.elf download.bit it will take the FPGA design (with soft cpu) and merge the elf file __into__ it. in Lattice flow you *can* do the same. in Altera flow this is ASFAIK __not_possible__ at all. What I need a very simple thing>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>my_design.sof + my_software.elf => my_ready_to_program.sof>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>I see no other way as doing full RE on the SOF to accomplish that. its stupid, and I would REALLY like to use Altera tools to do that, but if Altera is not able to provide such an important tool/option then someone has todo it (I really would prefer to spend my time with other things than doing RE on altera file formats) Antti
Reply by ●November 17, 20062006-11-17
Hi Antti, are you using "Smart Compilation" ? Plain Quartus: If you have a design compiled with "Smart Compilation" enabled, and then change just a memory-content-file and restart compilation, a magic "MIF/HEX Updater" (or similar) appears after the Fitter-process (which is skipped by smart compilation) and does what you want. I suppose this is also doable on the command-line. But don't ask me about the NIOS-tool-flow, you know, I am using ERIC5 ;-) Thomas "Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag news:1163790539.029200.67630@f16g2000cwb.googlegroups.com...> kem...@yahoo.com schrieb: > >> On Nov 17, 6:50 am, "Antti" <Antti.Luk...@xilant.com> wrote: >> > I just cant belive it, its one of the most useful things for the FPGA >> > SoC designs, and its just not there? I really doesnt have time or fun >> > to reverse engineer the .SOF format only to be able write the data2sof >> > utility for Altera. >> >> Antti, >> >> Others have commented on the general-purpose case, but since you made a >> specfiic reference to processors its worth discussing the soft-CPU flow >> for placing your code/data into onchip ram. >> >> No, this wasn't forgotten. In fact, support for doing this has been >> around about as long as Nios I/Nios II have been (6+ years now?). There >> are even >> several ways to accomplish the task: >> >> - If you are building your Nios II software in the IDE, it will take >> any coce/data linked into >> an onchip memory peripheral and use the elf2hex command to create a hex >> initialization >> file. The onchip RAM RTL generated by SOPC Builder is written out to be >> initialized this >> way; if you compile your design w/o any software having been built, >> memory will be left >> un-initialized, while if you first compile your software and then >> (re)compile in quartus, >> the .hex file(s) are used to initialize the memories. >> >> If you turn on verbose command line output from the IDE (window -> >> preferences -> nios II), >> you'll see the precise commands fly by on the console for future >> reference and command- >> line use. >> >> - Although the IDE-based flow doesn't do this now, you can even update >> your .sof >> file very quickly with onchip ram contents without risk of triggering >> an entire >> re-compile. I cannot recall the exact syntax of the command but I >> believe the compilation >> step is the Quartus Assembler (quartus_asm) >> >> - The "small" example design that ships with Nios II uses the above >> IDE-based >> method to initialize onchip RAM and as I recall the design's readme and >> other >> literature discuss this. >> >> Note that there are exclusions to what I've said, specifically for the >> types of >> onchip ram (m-ram blocks in Stratix, Stratix II) that cannot be >> initialized until >> runtime. The wizard to create an onchip ram in SOPC Builder allows you >> to >> choose which type of ram block will be used, if you desire, to ensure >> that you >> can pre-initialize contents if that is what you need to do. >> >> Jesse Kempa >> Altera Corp. >> jkempa --at-- altera --dot-- com > > Dear Jesse, > > I know about all you said above. but you missed the point. > > in Xilinx flow you can run a tool like: > > data2mem system.bit software.elf download.bit > > it will take the FPGA design (with soft cpu) and merge the elf file > __into__ it. > > in Lattice flow you *can* do the same. > > in Altera flow this is ASFAIK __not_possible__ at all. > > What I need a very simple thing > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > > my_design.sof + my_software.elf => my_ready_to_program.sof > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > > I see no other way as doing full RE on the SOF to accomplish that. > its stupid, and I would REALLY like to use Altera tools to do that, > but if Altera is not able to provide such an important tool/option > then someone has todo it (I really would prefer to spend my time > with other things than doing RE on altera file formats) > > Antti >
Reply by ●November 17, 20062006-11-17
Thomas Entner schrieb:> Hi Antti, > > are you using "Smart Compilation" ? > > Plain Quartus: If you have a design compiled with "Smart Compilation" > enabled, and then change just a memory-content-file and restart compilation, > a magic "MIF/HEX Updater" (or similar) appears after the Fitter-process > (which is skipped by smart compilation) and does what you want. I suppose > this is also doable on the command-line. But don't ask me about the > NIOS-tool-flow, you know, I am using ERIC5 ;-) > > Thomas >Thomas, I dont want smart recompile! I want NO COMPILE. Compile once. Merge new ELF file into the SOF file n - times. Antti
Reply by ●November 17, 20062006-11-17
Antti wrote:> Thomas Entner schrieb: > > >>Hi Antti, >> >>are you using "Smart Compilation" ? >> >>Plain Quartus: If you have a design compiled with "Smart Compilation" >>enabled, and then change just a memory-content-file and restart compilation, >>a magic "MIF/HEX Updater" (or similar) appears after the Fitter-process >>(which is skipped by smart compilation) and does what you want. I suppose >>this is also doable on the command-line. But don't ask me about the >>NIOS-tool-flow, you know, I am using ERIC5 ;-) >> >>Thomas >> > > Thomas, > I dont want smart recompile! I want NO COMPILE. > > Compile once. > > Merge new ELF file into the SOF file n - times.I think Antti is after a solution that does not need Full Quratus, but is just a 'insert code' step. As he says, simple enough, and surprising it is not there aready. There must be many teams, where the software is separate from the FPGA development, and it is both quicker and safer to avoid any rebuild of the FPGA. Maintenance/version control, is another area where this ability gets important. Could you not find the portion of Quartus that Jesse mentioned ? Amongst the choices, he said: " you can even update your .sof file very quickly with onchip ram contents without risk of triggering an entire re-compile. I cannot recall the exact syntax of the command but I believe the compilation step is the Quartus Assembler (quartus_asm)" - and hopefully, that command line is both a small EXE, and not needing a license install :) -jg
Reply by ●November 17, 20062006-11-17
"Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag news:1163796133.373645.327180@m7g2000cwm.googlegroups.com...> Thomas Entner schrieb: > >> Hi Antti, >> >> are you using "Smart Compilation" ? >> >> Plain Quartus: If you have a design compiled with "Smart Compilation" >> enabled, and then change just a memory-content-file and restart >> compilation, >> a magic "MIF/HEX Updater" (or similar) appears after the Fitter-process >> (which is skipped by smart compilation) and does what you want. I suppose >> this is also doable on the command-line. But don't ask me about the >> NIOS-tool-flow, you know, I am using ERIC5 ;-) >> >> Thomas >> > Thomas, > I dont want smart recompile! I want NO COMPILE. > > Compile once. > > Merge new ELF file into the SOF file n - times. > > Antti >OK, I think I just realized what you are looking for (it's late...): precompiled bitstream you give to the user, where the user's custom firmware can be merged into... (I asume for your MicroFPGAs, originally I was thinking you just want to save compile-time). Don't know... With ERIC, I have the programm in a part of the configuration-SPI-Flash, as the internal RAM is quite small anyway. But I can see your point, as you have only the CPU in the FPGA... Maybe quartus_asm can help you in a way (as Jesse mentioned above), but I am afraid, it will rely on some contents of the db-subdirectory? Thomas
