Virtex-4 DDR RAM Usage (with VHDL)

Hello,

I'm trying to access the DDR SDRAM of a Virtex-4 ML403 Evaluation board 
(XC4VFX12-10).

I downloaded the reference implementation from the Xilinx Homepage, 
removed the ICON and ILA parts and synthesized it. The upload to the 
FPGA worked without problems and it accessed the DDR RAM (at least the 
DDR RAM heated up).

After reading the reference design specification and the DDR RAM user 
guide the best point to start my own modifications and implement some 
primitive tests was the test_bench (mem_interface_top_test_bench_0.vhd).

I implemented a simple state machine controlled via the board's switches 
to understand the process step by step (precharge, write, read) [1].

Of course it didn't work, the basic problem is that the state machine 
does not switch the state. (If I synthesize just the state machine 
without the DDR RAM interface the state machine works fine.)


Is there a basic error in my approach to access the DDR RAM (in the 
sense of a wrong module as start point)?
Does anyone have a working example how to access the DDR RAM of a 
Virtex-4 Board using the reference implementation?


Thanks in advance,
Elmar Weber

[1] The code of the state machine with which I replaced the test bench 
is rather long, if anyone wants to take a look I can post it seperately.