Missing module : XFFT_V3_1 Verilog (not VHDL) module

Hello,

Does anyone know if XFFT_V3_1 Verilog (not VHDL) module (normally found
in C:\Modeltech_xe_starter\xilinx\verilog\XilinxCoreLib_ver) exists? It
was not shipped with ISE7.1i (I have noticed a few people in newsgroups
asking similar question), I got the update from Xilinx site but still
no luck. If you know, can you please point me to where to
-download it
-or compress and email it to me at vmykhayl@ee.ryerson.ca.

Regards,
Vitaliy

PS. The error message:
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps
design_top_tb_tf glbl
# Loading work.design_top_tb_tf
# Loading work.design_top
# ** Warning: (vsim-3009) [TSCALE] - Module 'design_top' does not have
a `timescale directive in effect, but previous modules do.
#         Region: /design_top_tb_tf/uut
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver.IBUFG
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver.DCM
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver.dcm_clock_divide_by_2
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver.dcm_maximum_period_check
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver.dcm_clock_lost
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver.BUFG
# Loading work.my_radix2_xfft1024
# ** Error: (vsim-3033) my_radix2_xfft1024.v(135): Instantiation of
'XFFT_V3_1' failed. The design unit was not found.
#         Region: /design_top_tb_tf/uut/U3
#         Searched libraries:
#
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/xilinxcorelib_ver
#
C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/unisims_ver
#             work