I probably will use a full-blown 32-bit CPU in my next project. And I was thinking if I could use the Lattice Mico32 Unfortunately, I haven't had time to get familiar with this CPU yet. I know however that more than a few of you have been playing with it, so I am asking for your impression so far. I will be very thankful if anyone can answer any of the following questions: - What do you think of the CPU so far? How does it compare to the alternatives? - In terms of size and speed, how does it compare to the competition? - How good is the software support (GCC) and how well designed is the HAL and low-level library connection? How well is the Wishbone interface working in practice? - If I plan to use a non-Lattice FPGA, would things work as smooth or will development become much more difficult? - How does the area & speed change across FPGA families and vendors? I remember that Mico8 became noticeably larger when targeting Cyclone and Spartan FPGAs... - Are any there any technical difficulties against porting Linux to this CPU? (just out of curiosity and completely unrelated to my project) thank you in advance, burns
Mico32, how good is it?
Started by ●November 26, 2006
Reply by ●November 26, 20062006-11-26
> - If I plan to use a non-Lattice FPGA, would things work as smooth or > will development become much more difficult?The only tricky bit will be the debugger, as that uses the dedicated Lattice JTAG block. Workaround that, and the rest should be no problem at all.> - Are any there any technical difficulties against porting Linux to > this CPU? (just out of curiosity and completely unrelated to my > project)It doesn't have an MMU, so the full blown Linux is out of the question. However, it should be relatively straight forward to port uCLinux. Cheers, Jon
Reply by ●November 27, 20062006-11-27
Thank you for your answer Jon, The JTAG problem was expected, and is easy to fix (write your own JTAG block). Regarding the MMU, well, I have heard the MB cannot be modified to include a MMU, is the same true for Mico32? The reason that I posted my previous questions in the first place was that if you synthesize a Mico32 project with, say, Quartus II you will notice that it cant fit in _any_ Cyclone II devices. The reason is that the lm32_ram block is designed in such way that the Quartus synthesizer cannot infer MK4 blocks... So my question to the list: has _anyone_ tried this CPU on Altera devices? regards, burns (still waiting for my ECP2M kit) Jon Beniston wrote:> > - If I plan to use a non-Lattice FPGA, would things work as smooth or > > will development become much more difficult? > > The only tricky bit will be the debugger, as that uses the dedicated > Lattice JTAG block. Workaround that, and the rest should be no problem > at all. > > > - Are any there any technical difficulties against porting Linux to > > this CPU? (just out of curiosity and completely unrelated to my > > project) > > It doesn't have an MMU, so the full blown Linux is out of the question. > However, it should be relatively straight forward to port uCLinux. > > Cheers, > Jon
Reply by ●November 27, 20062006-11-27
burn.sir@gmail.com schrieb:> Thank you for your answer Jon, > > > The JTAG problem was expected, and is easy to fix (write your own JTAG > block). Regarding the MMU, well, I have heard the MB cannot be modified > to include a MMU, is the same true for Mico32? > > > The reason that I posted my previous questions in the first place was > that if you synthesize a Mico32 project with, say, Quartus II you will > notice that it cant fit in _any_ Cyclone II devices. The reason is that > the lm32_ram block is designed in such way that the Quartus synthesizer > cannot infer MK4 blocks... > > > So my question to the list: has _anyone_ tried this CPU on Altera > devices? > > > regards, burns (still waiting for my ECP2M kit) >it works on Xilinx so should also work in A :) Antti
Reply by ●November 27, 20062006-11-27
No surprise there, Mico32 was Originally _designed_ for Xilinx FPGAs. burns Antti wrote:> it works on Xilinx so should also work in A :) > > Antti
Reply by ●November 27, 20062006-11-27
burn.sir@gmail.com schrieb:> No surprise there, Mico32 was Originally _designed_ for Xilinx FPGAs. > > > burns >hmm. I had a vision that it wasnt directly originated from Lattice ;) Antti
Reply by ●November 27, 20062006-11-27
burn.sir@gmail.com wrote:> No surprise there, Mico32 was Originally _designed_ for Xilinx FPGAs.And how would you know that? (Because it isn't true :-) ). Cheers, Jon
Reply by ●November 27, 20062006-11-27
burn.sir@gmail.com wrote:> Thank you for your answer Jon, > > > The JTAG problem was expected, and is easy to fix (write your own JTAG > block). Regarding the MMU, well, I have heard the MB cannot be modified > to include a MMU, is the same true for Mico32?You could add an MMU to Mico32. It would probably have to sit on the bus rather than in the pipeline though (unless you want to ripup the pipeline completely). So you have virtually tagged caches etc. You could either use the user defined instructions for updating the TLB, or just memory map them. Cheers, Jon
Reply by ●November 28, 20062006-11-28
Just one thing, MicroBlaze can of course have a MMU. Wonder what the idea this it's impossible come from? G�ran Bilski <burn.sir@gmail.com> wrote in message news:1164647777.560172.119220@f16g2000cwb.googlegroups.com...> Thank you for your answer Jon, > > > The JTAG problem was expected, and is easy to fix (write your own JTAG > block). Regarding the MMU, well, I have heard the MB cannot be modified > to include a MMU, is the same true for Mico32? > > > The reason that I posted my previous questions in the first place was > that if you synthesize a Mico32 project with, say, Quartus II you will > notice that it cant fit in _any_ Cyclone II devices. The reason is that > the lm32_ram block is designed in such way that the Quartus synthesizer > cannot infer MK4 blocks... > > > So my question to the list: has _anyone_ tried this CPU on Altera > devices? > > > regards, burns (still waiting for my ECP2M kit) > > Jon Beniston wrote: >> > - If I plan to use a non-Lattice FPGA, would things work as smooth or >> > will development become much more difficult? >> >> The only tricky bit will be the debugger, as that uses the dedicated >> Lattice JTAG block. Workaround that, and the rest should be no problem >> at all. >> >> > - Are any there any technical difficulties against porting Linux to >> > this CPU? (just out of curiosity and completely unrelated to my >> > project) >> >> It doesn't have an MMU, so the full blown Linux is out of the question. >> However, it should be relatively straight forward to port uCLinux. >> >> Cheers, >> Jon >
Reply by ●November 28, 20062006-11-28
So G�ran, When will it be ready ;-) Lattice is already talking about that a MMU is on it's way.. Regards Finn "G�ran Bilski" <goran.bilski@xilinx.com> skrev i en meddelelse news:ekgq4k$t8d2@cnn.xsj.xilinx.com...> Just one thing, MicroBlaze can of course have a MMU. > Wonder what the idea this it's impossible come from? > > G�ran Bilski > > <burn.sir@gmail.com> wrote in message > news:1164647777.560172.119220@f16g2000cwb.googlegroups.com... >> Thank you for your answer Jon, >> >> >> The JTAG problem was expected, and is easy to fix (write your own JTAG >> block). Regarding the MMU, well, I have heard the MB cannot be modified >> to include a MMU, is the same true for Mico32? >> >> >> The reason that I posted my previous questions in the first place was >> that if you synthesize a Mico32 project with, say, Quartus II you will >> notice that it cant fit in _any_ Cyclone II devices. The reason is that >> the lm32_ram block is designed in such way that the Quartus synthesizer >> cannot infer MK4 blocks... >> >> >> So my question to the list: has _anyone_ tried this CPU on Altera >> devices? >> >> >> regards, burns (still waiting for my ECP2M kit) >>
