I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am having trouble with the verilog model. I have used both a samsung and a micron model for the part (two compatible parts). Unfortunately these models are not available in VHDL, and my verilog is pretty weak. I wondered if any one had some experience with memory models, both in terms of using them to design memory controllers and debugging them when they spit out spurious timing violations. These verilog models in particular seem to send out all manner of timing violations or functional problems that don't seem to be in line at all with what the data sheet says regarding the timing and command and control procedures (for doing a full page read or write, for instance). Has any one else had trouble with bad/buggy models? What is the best way to solve this problem? What is the best way to go about designing a memory controller (I have seen an example on Altera's website in VHDL (but it sucks), as well as some others in open cores and one written for a homebrew graphics accelerator card (manticore). I find the documentation and/or functionality lacking in most of the aforementioned existing reference designs. thanks
problems with verilog SDRAM models
Started by ●November 27, 2006
Reply by ●November 27, 20062006-11-27
In my experience, the Micron models are very very good. I did find a subtle bug in one of their DDR SDRAM models, but it did not affect normal behaviour, and they fixed it as soon as it was brought to their attention. There are SDR SDRAM VHDL models available from Micron. The differences between one 4-band SDRAM and another 4-bank SDRAM are mote, so just pick one and go with it. GH
Reply by ●November 28, 20062006-11-28
ghelbig@lycos.com wrote:> In my experience, the Micron models are very very good. I did find a > subtle bug in one of their DDR SDRAM models, but it did not affect > normal behaviour, and they fixed it as soon as it was brought to their > attention. > > There are SDR SDRAM VHDL models available from Micron. The differences > between one 4-band SDRAM and another 4-bank SDRAM are mote, so just > pick one and go with it. > > GHcurrently I m doing the interface between SDRAM and FPGA. but Controller is using VHDL. I have written my own code refering to a couple of verilog cores. I am facing problem in accessing another bank of same row simultaneuosly. I require a page burst of more than the columns available in single bank. Help me pls if you can. thanks, MDA.
Reply by ●November 28, 20062006-11-28
Hi, you can try to finde any equivalent models at hynix or quimonda (former infinion). Or use freemodelfoundry.com. I had the same problem, because Xilinix Memory Interface Generator also provided verilog only models. Bye Helmut wallge wrote:> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanks
Reply by ●November 28, 20062006-11-28
You can also look here: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/4312c0a1e204ced2/c2cc389ee809ce7d?hl=en#c2cc389ee809ce7d Bye Helmut
Reply by ●November 28, 20062006-11-28
wallge wrote:> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanksHi, I'm trying to use an AMD (Spansion) FLASH model, and it's just one BIG headache. Despite following all their advice and recompiling lots of libraries with vital2000, the model still falls over immediately in modelsim. It's really poor putting out models that just don't work, IMO. Kev P.
Reply by ●November 28, 20062006-11-28
On 27 Nov 2006 14:54:21 -0800, "wallge" <wallge@gmail.com> wrote:>I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM >that I want to be able to control via an FPGA on the same PCB. >I am having trouble with the verilog model. I have used both a samsung >and a micron model for the part (two compatible parts). Unfortunately >these models are not available in VHDL, and my verilog is pretty weak.Micron certainly used to provide good VHDL models, and I wish they still did. Look for an older non-mobile equivalent for the SDRAM (same size, bus width, banks, etc and same speed grade if possible) and you'll probably find a VHDL model for it. Failing that, Hynix provide VHDL models, but I don't know if they have an equivalent part to the mobile SDRAM you are using. - Brian
Reply by ●December 3, 20062006-12-03
Kev, Please contact me through the FMF website. We have received no bug reports on this model. Although the VITAL2000 issue is common, it is limited to modelsim. I will help you workout whatever other issues you have. If there is an actual bug, we are under contract from Spansion to fix it. Rick Munden Niv wrote:> wallge wrote: >> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM >> that I want to be able to control via an FPGA on the same PCB. >> I am having trouble with the verilog model. I have used both a samsung >> and a micron model for the part (two compatible parts). Unfortunately >> these models are not available in VHDL, and my verilog is pretty weak. >> >> I wondered if any one had some experience with memory models, both in >> terms of using them to design memory controllers and debugging them >> when they spit out spurious timing violations. >> These verilog models in particular seem to send out all manner of >> timing violations or functional problems that don't seem to be in line >> at all with what the data sheet says regarding the timing and command >> and control procedures (for doing a full page read or write, for >> instance). >> >> Has any one else had trouble with bad/buggy models? What is the best >> way to solve this problem? >> What is the best way to go about designing a memory controller (I have >> seen an example on Altera's website in VHDL (but it sucks), as well as >> some others in open cores and one written for a homebrew graphics >> accelerator card (manticore). I find the documentation and/or >> functionality lacking in most of the aforementioned existing reference >> designs. >> >> thanks > > Hi, I'm trying to use an AMD (Spansion) FLASH model, and it's just one > BIG headache. > Despite following all their advice and recompiling lots of libraries > with vital2000, the model > still falls over immediately in modelsim. > > It's really poor putting out models that just don't work, IMO. > > Kev P. >
Reply by ●December 3, 20062006-12-03
What partnumber do you need to simulate? wallge wrote:> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanks >
Reply by ●December 4, 20062006-12-04
wallge wrote:> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak.... I used a Verilog Micron model to develop my DDR/DDR2 controller and was very happy with the model. I had to set a couple of `defparams to make the model match my hardware, and it was very helpful in reporting all timing errors, such as violations in write recovery time, etc. There is a "Debug" parameter you can switch on to report all data transactions as well. Before you write your own controller, though, I warn you that it is much more difficult than you anticipate. -Kevin