Is the P&R processing time proportional to the FPGA gate count or the size of my logic?

Hi, there:

I am performing active-module P&R for partial reconfiguration. My fixed
logic is 30K (ASIC) gates, and the
variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable
modules with a blackbox
for fixed module, how come it takes over 30 minutes but still ISE 6.1
couldn't finish this small module.

I want to know whether the P&R time is more related to my chip size OR the
size of my FPGA(Virtex2, 6000K).

Besides that, how may I derive the output file names in multi-pass P&R, e.g.
4_4_1.ncd from my par command
options?


Best Regards,
Kelvin

PAR time is related to many factors including the complexity of your design and
aggressiveness of the timing constraints relative to the logic delays in your
design.  Good floorplanning can reduce an 8 hour run to a few minutes (I've got
a fairly sparse - 25% utilized 2V6000 I am working with right now)  without
placing the BRAMs, I ws getting PAR runs in the 8-10 hour range.  By simply
placing the BRAMs and the output pipeline registers using floorplanning, it
reduces the par time to under 20 minutes.

"Kelvin @ SG" wrote:

> Hi, there:
>
> I am performing active-module P&R for partial reconfiguration. My fixed
> logic is 30K (ASIC) gates, and the
> variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable
> modules with a blackbox
> for fixed module, how come it takes over 30 minutes but still ISE 6.1
> couldn't finish this small module.
>
> I want to know whether the P&R time is more related to my chip size OR the
> size of my FPGA(Virtex2, 6000K).
>
> Besides that, how may I derive the output file names in multi-pass P&R, e.g.
> 4_4_1.ncd from my par command
> options?
>
> Best Regards,
> Kelvin

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

> I am performing active-module P&R for partial reconfiguration. My fixed
> logic is 30K (ASIC) gates, and the
> variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable
> modules with a blackbox
> for fixed module, how come it takes over 30 minutes but still ISE 6.1
> couldn't finish this small module.

It sounds like you have very aggressive timing specs.  How fast are you
clocking your FPGA?  There should be a *.par report file that gives you some
details about your design.  Does it show your design having many levels of
logic?

I've never done ASIC design, but perhaps you folks don't use flip-flops a
lot.  FFs are "free" in FPGAs so we tend to stick as many of them into our
datapaths as we can.  I habitually stick in FFs after only a couple levels
of logic, if I can afford the latency.  Sometimes I'll throw in one right
after a single AND gate because it's "free".

> I want to know whether the P&R time is more related to my chip size OR the
> size of my FPGA(Virtex2, 6000K).

By "chip size" do you mean "design size"?  I don't think the capacity of
your FPGA makes a difference, unless your design is close to 100%
utilization, then the tools have less room to work, on top of more routing
congestion.

Having too much space might also be a problem if the tools place your logic
far apart just because they can.  If you see it doing that (by looking with
Floorplanner) you might want to set an area constraint to force your logic
into a reasonable area..

The speed grade (e.g. -6,-7,...) of your FPGA might be more of an issue than
size.


Regards,
Vinh Pham
vinh-pham (a) hawaii rr com

Thank you all for your response. Now I understand that for same design the
run time and RAM usage do
increase with the FPGA cip size.

Best Regards,
Kelvin




"Ray Andraka" <ray@andraka.com> wrote in message
news:3FFBAAEC.D224DF2F@andraka.com...
> PAR time is related to many factors including the complexity of your
design and
> aggressiveness of the timing constraints relative to the logic delays in
your
> design.  Good floorplanning can reduce an 8 hour run to a few minutes
(I've got
> a fairly sparse - 25% utilized 2V6000 I am working with right now)
without
> placing the BRAMs, I ws getting PAR runs in the 8-10 hour range.  By
simply
> placing the BRAMs and the output pipeline registers using floorplanning,
it
> reduces the par time to under 20 minutes.
>
> "Kelvin @ SG" wrote:
>
> > Hi, there:
> >
> > I am performing active-module P&R for partial reconfiguration. My fixed
> > logic is 30K (ASIC) gates, and the
> > variable logic modules are 0.5 & 2K gates only...Now I am P&R the
variable
> > modules with a blackbox
> > for fixed module, how come it takes over 30 minutes but still ISE 6.1
> > couldn't finish this small module.
> >
> > I want to know whether the P&R time is more related to my chip size OR
the
> > size of my FPGA(Virtex2, 6000K).
> >
> > Besides that, how may I derive the output file names in multi-pass P&R,
e.g.
> > 4_4_1.ncd from my par command
> > options?
> >
> > Best Regards,
> > Kelvin
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>