Opencores DDR SDRAM controller

Hello to all,

I'm new in this forum; In a Project I need to write and read from a
Micron DDR memory (I have a Spartan 3E starter kit wit a Micron
46V32M16); I tried to use the Opencores DDR Sdram controller and the
simulation with my code was fine (the ddr controller is for a 46V16M16
but I see that the only difference is the half memory space).
When I try to Implement the code in the board the controller don't work
properly; I write some data in different address but I read alwais the
last data writted.
I use the Xilinx ISE Webpack 8.2.03i.
May sameone help me please?
Thanks in advance for all.

Daniele

Well, you have to use some more effort. Use Chipscope (or a logic
analyser) for hardware debug and watch IO signals to/from SDR.
If your simulation works for only half of memory than you are missing
one address line.

Cheers,

guru

cippalippa wrote:
> Hello to all,
>
> I'm new in this forum; In a Project I need to write and read from a
> Micron DDR memory (I have a Spartan 3E starter kit wit a Micron
> 46V32M16); I tried to use the Opencores DDR Sdram controller and the
> simulation with my code was fine (the ddr controller is for a 46V16M16
> but I see that the only difference is the half memory space).
> When I try to Implement the code in the board the controller don't work
> properly; I write some data in different address but I read alwais the
> last data writted.
> I use the Xilinx ISE Webpack 8.2.03i.
> May sameone help me please?
> Thanks in advance for all.
> 
> Daniele

Did you use a simulation model for you memory module?

Yes, I use the simulation model that I found with opencores IP; and
with this model the controller work perfectly.
When I implement the core and I downloaded the bitstream in the FPGA
the controller don't work.
The memory that I have isn't the same of the simulation model but the
version with duble memory; this memory however have identical timing so
if I use half memory I think that the memory must work.
When I try to write and read from this memory I only read always the
last data writted.


Vangelis ha scritto:

> Did you use a simulation model for you memory module?

cippalippa wrote:
> Hello to all,
>
> I'm new in this forum; In a Project I need to write and read from a
> Micron DDR memory (I have a Spartan 3E starter kit wit a Micron
> 46V32M16); I tried to use the Opencores DDR Sdram controller and the
> simulation with my code was fine (the ddr controller is for a 46V16M16
> but I see that the only difference is the half memory space).
> When I try to Implement the code in the board the controller don't work
> properly; I write some data in different address but I read alwais the
> last data writted.
> I use the Xilinx ISE Webpack 8.2.03i.
> May sameone help me please?
> Thanks in advance for all.
>
> Daniele

As far as I know, the Xilinx Webpack can generate Memory Controller
according to the given parameters like bus width etc. So there is no
need to write your own controller anymore, except you want to optimize
something specific to your application.


Steven

cippalippa wrote:

> When I try to Implement the code in the board the controller don't work
> properly; I write some data in different address but I read alwais the
> last data writted.

Do you use a clock of 133 MHz? Xilinx provides a reference design, which
works with an external 133 MHz clock:

http://www.xilinx.com/support/software/memory/protected/index.htm

If it doesn't produce too much jitter, maybe it works with a DCM generated
133 MHz clock from the on-board 50 MHz clock, too?

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Hi,

thanks for the answer.
However I already see the Xilinx reference design but I have a bad
experience with this kind of design.
I don't need particular performace; 100 MHz speed and burst 2 for me is
enaught.
I see that opencores IP seems simple and Xilinx IP with MIG seems
complicate; I ask to Xilinx Field Application engineer if this IP
generated from Xilinx MIG works and they ask me: "I don't know"; so if
I'm not sure that this controller work I prefer to use Opencore IP.
Sameone have already use the Opencore DDR sdram controller? If so how I
must modify the design for the sintesis?
Thanks

Daniele

cippalippa wrote:
> thanks for the answer.
> However I already see the Xilinx reference design but I have a bad
> experience with this kind of design.
> I don't need particular performace; 100 MHz speed and burst 2 for me is
> enaught.
> I see that opencores IP seems simple and Xilinx IP with MIG seems
> complicate; I ask to Xilinx Field Application engineer if this IP
> generated from Xilinx MIG works and they ask me: "I don't know"; so if
> I'm not sure that this controller work I prefer to use Opencore IP.
> Sameone have already use the Opencore DDR sdram controller? If so how I
> must modify the design for the sintesis?

Maybe I misunderstood, but it already does synthesize. David Ashley, as
posted here earlier, did the needed modification to get it running on
the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on
Digilent's Spartan 3E1600 board.

That said, the Opencore DDR controller is not perfect, but it's a good
starting point for verifying that the basic .ucf constaints are set up
(mostly) correctly.

Tommy

Tommy Thorn wrote:

> Maybe I misunderstood, but it already does synthesize. David Ashley, as
> posted here earlier, did the needed modification to get it running on
> the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on
> Digilent's Spartan 3E1600 board.

Do you have a link to a working project or the ucf file? I would like to
use the DDR SDRAM, too, but I can't find the posting.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Frank Buss wrote:
> Tommy Thorn wrote:
>
> > Maybe I misunderstood, but it already does synthesize. David Ashley, as
> > posted here earlier, did the needed modification to get it running on
> > the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on
> > Digilent's Spartan 3E1600 board.
>
> Do you have a link to a working project or the ucf file? I would like to
> use the DDR SDRAM, too, but I can't find the posting.

Sorry, it was a bit tricky to find. The original thread:
http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/a58600c317356edb/27f9d22a4590952b?rnum=11&q=david+ashley+ddr&_done=%2Fgroup%2Fcomp.arch.fpga%2Fbrowse_frm%2Fthread%2Fa58600c317356edb%2F979d5e1695dc1710%3Flnk%3Dst%26q%3Ddavid+ashley+ddr%26rnum%3D2%26#doc_27f9d22a4590952b

For your convienience, the source (quoting David: "It's a pretty much
identical copy of the open cores ddr controller, except I removed one
DCM, and I wrapped it all in a synthesizable tester targeted to the
spartan-3e starter board."): http://www.xdr.com/dash/fpga/

My humble contribution: a complete constraints file for the Digilent
Spartan 3E-1600 Development Board (aka. Spartan 3E starter kit in the
XC3S1600E edition): http://not.meko.dk/spe1600e-1.1.ucf

Please share any improvements or suggestions.

Tommy