Free Anydivider, Divide clock by any number

Hi,
I have just finished this free commercial grade tool. I wish it is
useful.
Topweaver Anydivider (TAD) is a GUI based EDA tool to generate a
divided output clock (frequency = Fout) based on an input clock
(frequency = Fin), without a DLL/PLL. The waveform of the output clock
can be either from automatical calculation or from visual adjustment.
Fout=Fin * M / N
TAD can analyze the relation of duty cycle and jitter.
The generated code are written by verilog. Thanks to the mixed-language
feature of most EDA tools, VHDL user can use it directly.
For more features, please visit
http://www.topweaver.com/doc/tad/tad.htm
Download http://www.topweaver.com/download.htm

This sounded interesting until I saw the output.
It is not a frequency of pulses, but rather the incoming pulse-stream
with the appropriate number of pulses deleted. That means a big jitter
(except for the trivial cases of integer division) and a broad
spectrum.
If that is acceptable, your solution is still not optimal, as shown in
your example of 4/11, which could have a better spectrum than the one
you provide.
A good solution should only delete n and n-1 consecutive pulses.
Peter Alfke

On Dec 5, 6:34 am, topwea...@hotmail.com wrote:
> Hi,
> I have just finished this free commercial grade tool. I wish it is
> useful.
> Topweaver Anydivider (TAD) is a GUI based EDA tool to generate a
> divided output clock (frequency = Fout) based on an input clock
> (frequency = Fin), without a DLL/PLL. The waveform of the output clock
> can be either from automatical calculation or from visual adjustment.
> Fout=Fin * M / N
> TAD can analyze the relation of duty cycle and jitter.
> The generated code are written by verilog. Thanks to the mixed-language
> feature of most EDA tools, VHDL user can use it directly.
> For more features, please visithttp://www.topweaver.com/doc/tad/tad.htm
> Downloadhttp://www.topweaver.com/download.htm

Hi Peter Alfke,
Thanks for viewing Topweaver Anydivider (TAD).
In fact the feature you said has been realized by TAD. And it is only a
part of TAD. If TAD can only generate the "n and n-1 consecutive
pulses", I can not name it ANY.
The waveform of the output clock can be either from automatical
calculation or from visual adjustment.
The example of 4/11 is in manual mode, to illustrate how to drag the
waveform to anything you want. And the performance report shows a
jitter of 22.40437%.
"A good solution" can be generated in the auto mode, which is shown in
the first picture.
A strong point of TAD is the powerful analysis ability, which can help
the engineers to choose the best waveform.

TAD

"Peter Alfke =D0=B4=B5=C0=A3=BA
"
> This sounded interesting until I saw the output.
> It is not a frequency of pulses, but rather the incoming pulse-stream
> with the appropriate number of pulses deleted. That means a big jitter
> (except for the trivial cases of integer division) and a broad
> spectrum.
> If that is acceptable, your solution is still not optimal, as shown in
> your example of 4/11, which could have a better spectrum than the one
> you provide.
> A good solution should only delete n and n-1 consecutive pulses.
> Peter Alfke
>

topweaver@hotmail.com wrote:
> Hi Peter Alfke,
> Thanks for viewing Topweaver Anydivider (TAD).
> In fact the feature you said has been realized by TAD. And it is only a
> part of TAD. If TAD can only generate the "n and n-1 consecutive
> pulses", I can not name it ANY.
> The waveform of the output clock can be either from automatical
> calculation or from visual adjustment.
> The example of 4/11 is in manual mode, to illustrate how to drag the
> waveform to anything you want. And the performance report shows a
> jitter of 22.40437%.
> "A good solution" can be generated in the auto mode, which is shown in
> the first picture.
> A strong point of TAD is the powerful analysis ability, which can help
> the engineers to choose the best waveform.
>
> TAD
>
> "Peter Alfke =D0=B4=B5=C0=A3=BA
> "
> > This sounded interesting until I saw the output.
> > It is not a frequency of pulses, but rather the incoming pulse-stream
> > with the appropriate number of pulses deleted. That means a big jitter
> > (except for the trivial cases of integer division) and a broad
> > spectrum.
> > If that is acceptable, your solution is still not optimal, as shown in
> > your example of 4/11, which could have a better spectrum than the one
> > you provide.
> > A good solution should only delete n and n-1 consecutive pulses.
> > Peter Alfke
> >

Very interesting program.  I have a suggestion for code implementation
to work better in Xilinx (and possibly other) FPGA's.  Your code uses
clock gating to generate narrow pulses.  At least in Xilinx FPGA's it
is
not a good assumption that the Q output of a flip-flop has a longer
delay to the gate input than the clock does.  In fact, depending on the
placement, a route from a global clock to a LUT input can be several
nanoseconds.  This can cause glitches even when you use the
"correct" phase of the clock in your output logic.  I would suggest
using only flip-flop outputs to generate the module output, using
XOR functions as necessary to generate outputs using both clock
edges.  The global clock routing to the flip-flop clocks is much better
than you can do routing a global clock to a LUT input (or flip-flop D).

For waveforms that change on both input clock edges, It should
be possible to generate the output as the XOR of just two flip-flops,
one clocked on each edge.  One of the flip-flops would toggle at each
edge in the output waveform.  At higher input clock rates this method
also gives improved duty cycle accuracy, as the clock to output path
on each edge looks like one flip-flop clock to Q delay followed by one
LUT delay.  Differences in clock-to-Q for rising vs falling edge
flip-flops
are small compared to routing delays in the FPGA.

Regars,
Gabor

Let me explain what I mean with n and n-1.

If you want to reduce the number of pulses per unit time (that's what
you are doing) you do that by eliminating pulses from the input stream.
You can achieve ANY desired result by a pattern of eliminated pulses.
I claim that this pattern can achieve the desired result best when the
number of adjacently eliminated pulses never varies by more than one.
If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent
pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but
never with a mixture of 3, 4, and 5 adjacent pulses. There is no need
for it mathematically.
Peter Alfke

On Dec 6, 8:03=C2=A0am, topwea...@hotmail.com wrote:
> Hi Peter Alfke,
> Thanks for viewing Topweaver Anydivider (TAD).
> In fact the feature you said has been realized by TAD. And it is only a
> part of TAD. If TAD can only generate the "n and n-1 consecutive
> pulses", I can not name it ANY.
> The waveform of the output clock can be either from automatical
> calculation or from visual adjustment.
> The example of 4/11 is in manual mode, to illustrate how to drag the
> waveform to anything you want. And the performance report shows a
> jitter of 22.40437%.
> "A good solution" can be generated in the auto mode, which is shown in
> the first picture.
> A strong point of TAD is the powerful analysis ability, which can help
> the engineers to choose the best waveform.
>
> TAD
>
> "Peter Alfke =E5=86=99=E9=81=93=EF=BC=9A
> "
>
> > This sounded interesting until I saw the output.
> > It is not a frequency of pulses, but rather the incoming pulse-stream
> > with the appropriate number of pulses deleted. That means a big jitter
> > (except for the trivial cases of integer division) and a broad
> > spectrum.
> > If that is acceptable, your solution is still not optimal, as shown in
> > your example of 4/11, which could have a better spectrum than the one
> > you provide.
> > A good solution should only delete n and n-1 consecutive pulses.
> > Peter Alfke

"Peter Alfke" <peter@xilinx.com> writes:
>Let me explain what I mean with n and n-1.
>
>If you want to reduce the number of pulses per unit time (that's what
>you are doing) you do that by eliminating pulses from the input stream.
>You can achieve ANY desired result by a pattern of eliminated pulses.
>I claim that this pattern can achieve the desired result best when the
>number of adjacently eliminated pulses never varies by more than one.
>If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent
>pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but
>never with a mixture of 3, 4, and 5 adjacent pulses. There is no need
>for it mathematically.

Sounds to me like the good old SN7497 "binary rate multiplier".

-- 
         Georg Acher, acher@in.tum.de
         http://www.lrr.in.tum.de/~acher
         "Oh no, not again !" The bowl of petunias

Georg Acher wrote:

> "Peter Alfke" <peter@xilinx.com> writes:
> 
>>Let me explain what I mean with n and n-1.
>>
>>If you want to reduce the number of pulses per unit time (that's what
>>you are doing) you do that by eliminating pulses from the input stream.
>>You can achieve ANY desired result by a pattern of eliminated pulses.
>>I claim that this pattern can achieve the desired result best when the
>>number of adjacently eliminated pulses never varies by more than one.
>>If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent
>>pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but
>>never with a mixture of 3, 4, and 5 adjacent pulses. There is no need
>>for it mathematically.
> 
> 
> Sounds to me like the good old SN7497 "binary rate multiplier".

Yup.
  Rate multipliers also make good DACs, if you want DC from a
RC integrator. Smaller to code than PWM, and higher frequency corner.
-jg

If you want nostaglia:
I wrote this up in the 1972 Fairchild" TTL Applications Handbook" on
page 4-12 as application for the 9318 Priority Encoder.
As the French say: Plus ca change, plus c'est la meme chose
(pardon the missing accents)
Peter Alfke
=================
Jim Granville wrote:
> Georg Acher wrote:
>
> > "Peter Alfke" <peter@xilinx.com> writes:
> >
> >>Let me explain what I mean with n and n-1.
> >>
> >>If you want to reduce the number of pulses per unit time (that's what
> >>you are doing) you do that by eliminating pulses from the input stream.
> >>You can achieve ANY desired result by a pattern of eliminated pulses.
> >>I claim that this pattern can achieve the desired result best when the
> >>number of adjacently eliminated pulses never varies by more than one.
> >>If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent
> >>pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but
> >>never with a mixture of 3, 4, and 5 adjacent pulses. There is no need
> >>for it mathematically.
> >
> >
> > Sounds to me like the good old SN7497 "binary rate multiplier".
>
> Yup.
>   Rate multipliers also make good DACs, if you want DC from a
> RC integrator. Smaller to code than PWM, and higher frequency corner.
> -jg

Hi Peter Alfke,
I think we are describing the same thing.
In the first picture (http://www.topweaver.com/doc/tad/images/ov1.jpg),
the "Clock Out" has only the length of 5 and 6, which is you wanted.
And sometimes people may need a large jitter clock, or just a flag of
some time slot (not used for clock), they can drag the waveform to
anything they want in the manual mode.
TAD

"Peter Alfke =D0=B4=B5=C0=A3=BA
"
> Let me explain what I mean with n and n-1.
>
> If you want to reduce the number of pulses per unit time (that's what
> you are doing) you do that by eliminating pulses from the input stream.
> You can achieve ANY desired result by a pattern of eliminated pulses.
> I claim that this pattern can achieve the desired result best when the
> number of adjacently eliminated pulses never varies by more than one.
> If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent
> pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but
> never with a mixture of 3, 4, and 5 adjacent pulses. There is no need
> for it mathematically.
> Peter Alfke

Hi Gabor,
Thanks very much for your suggestion. Maybe I can fulfill it at this
weekend. Before the new release, I will post the sample generated
verilog code here.
TAD

"Gabor =D0=B4=B5=C0=A3=BA
"
> Very interesting program.  I have a suggestion for code implementation
> to work better in Xilinx (and possibly other) FPGA's.  Your code uses
> clock gating to generate narrow pulses.  At least in Xilinx FPGA's it
> is
> not a good assumption that the Q output of a flip-flop has a longer
> delay to the gate input than the clock does.  In fact, depending on the
> placement, a route from a global clock to a LUT input can be several
> nanoseconds.  This can cause glitches even when you use the
> "correct" phase of the clock in your output logic.  I would suggest
> using only flip-flop outputs to generate the module output, using
> XOR functions as necessary to generate outputs using both clock
> edges.  The global clock routing to the flip-flop clocks is much better
> than you can do routing a global clock to a LUT input (or flip-flop D).
>
> For waveforms that change on both input clock edges, It should
> be possible to generate the output as the XOR of just two flip-flops,
> one clocked on each edge.  One of the flip-flops would toggle at each
> edge in the output waveform.  At higher input clock rates this method
> also gives improved duty cycle accuracy, as the clock to output path
> on each edge looks like one flip-flop clock to Q delay followed by one
> LUT delay.  Differences in clock-to-Q for rising vs falling edge
> flip-flops
> are small compared to routing delays in the FPGA.
>=20
> Regars,
> Gabor