I apologize if this questions has been answered already. I was unable to find an answer in my search through this group. If you have any experience using LVDS with Xilinx FPGAs, please help. Q: If I have a LVDS input, must my top-level entity specify both the N and P ports, or is there a way to specify that a port should use LVDS in a constraint file and have the Xilinx tools infer the correct buffers? I know something to this effect works: ... input_p : std_logic; input_n : std_logic; ... port map ( I => input_p, IB => input_n, O => internal_single_ended_signal); But, is there a way to just have the following (plus specify that input is LVDS in a constraints file) and have the xilinx tools infer what is in the code above?: ... input : std_logic; ... Thank you in advance for your help.
help with Xilinx LVDS syntax
Started by ●December 6, 2006
Reply by ●December 6, 20062006-12-06
The port mapping must specify p and n sides of the input as you have done. The UCF needs to have the IOSTANDARD = LVDS_x set and only the P side pin needs a LOC constraint. The tools will pick up the IO standard correctly and place the N side on the correct corresponding P pin. "Morgan" <morgank@lanl.gov> wrote in message news:1165424528.893445.244150@l12g2000cwl.googlegroups.com...>I apologize if this questions has been answered already. I was unable > to find an answer in my search through this group. > > If you have any experience using LVDS with Xilinx FPGAs, please help. > > Q: If I have a LVDS input, must my top-level entity specify both the N > and P ports, or is there a way to specify that a port should use LVDS > in a constraint file and have the Xilinx tools infer the correct > buffers? > > I know something to this effect works: > > ... > input_p : std_logic; > input_n : std_logic; > ... > port map ( > I => input_p, > IB => input_n, > O => internal_single_ended_signal); > > > But, is there a way to just have the following (plus specify that input > is LVDS in a constraints file) and have the xilinx tools infer what is > in the code above?: > > ... > input : std_logic; > ... > > > Thank you in advance for your help. >