JTAG programming of Altera Cyclone and CONF_DONE

All,

I'm having an extraoridnarily difficult time with my first FPGA project and 
am very frustrated.

I have a board designed around the EP1C6 Cyclone device. The Quartus 
programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able to 
initiate programming the device over the JTAG port, but Quartus gives me an 
error CONF_DONE failed to go high on device 1.

I reviewed the Cyclone datasheet, and 13-19 in particular, "JTAG 
Configuration of Single Cyclone FPGA."

This diagram does not show CONF_DONE going to the programming header.

Why is Quartus complaining that CONF_DONE isn't going high when that signal 
isn't supposed to go to the programming header? More importantly, is there 
anything I can do to circumvent this problem?

Many thanks,

-Nevo 

Nevo wrote:
> Why is Quartus complaining that CONF_DONE isn't going high when that signal 
> isn't supposed to go to the programming header? More importantly, is there 
> anything I can do to circumvent this problem?

Quartus, using JTAG, can read the state of this pin without it having to 
be run to the header.

Break out the scope and connect it to CONF_DONE. Does it go high? If 
not, then the FPGA is not properly configured. This can be caused by a 
faulty JTAG connection, something holding CONF_DONE low, etc.

Marc

Nevo,

I'm not sure if you're using a development board or a board designed by you, 
but the CONF_DONE needs to have an external pull-up on the board.

What is the mode of configuration? What are you using for your configuration 
device?

Rob

"Nevo" <nevo_n@hotmail.com> wrote in message 
news:SmCeh.122$495.9@trnddc06...
> All,
>
> I'm having an extraoridnarily difficult time with my first FPGA project 
> and am very frustrated.
>
> I have a board designed around the EP1C6 Cyclone device. The Quartus 
> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able 
> to initiate programming the device over the JTAG port, but Quartus gives 
> me an error CONF_DONE failed to go high on device 1.
>
> I reviewed the Cyclone datasheet, and 13-19 in particular, "JTAG 
> Configuration of Single Cyclone FPGA."
>
> This diagram does not show CONF_DONE going to the programming header.
>
> Why is Quartus complaining that CONF_DONE isn't going high when that 
> signal isn't supposed to go to the programming header? More importantly, 
> is there anything I can do to circumvent this problem?
>
> Many thanks,
>
> -Nevo
> 

I had similar problems with a cyclone II device. The problem was, that
the CD came up to late according to the capacitve load caused by
another device the micro controller doing passive serial mode
configuration) listening to that pin.

Nevo wrote:

> I have a board designed around the EP1C6 Cyclone device. The Quartus 
> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able to 
> initiate programming the device over the JTAG port, but Quartus gives me an 
> error CONF_DONE failed to go high on device 1.

Interesting that you have these problems...

I have very recently inherited a board which I am using for a very
different purpose to that for which it was originally intended. The
board is based on an EP2C35 and has options for both passive and active
serial configuration, as well as JTAG. The former options require
configuration devices to be plugged into DIP sockets on the board.

Not needing auto-configuration, I dispatched with the config devices (I
actually don't *own* any) but was met with "CONF_DONE not going high"
when attempting to configure via JTAG.

After scratching my head for some time, I eventually tried it with the
config device plugged in - and it worked!

Now I can't for the life of me understand why this device must be
present for JTAG programming? There's a pullup on CONF_DONE (10k)and
nSTATUS (10k).

What's more, at one stage I configured the FPGA then removed the config
device whilst still powered - and I'm pretty sure a subsequent attempt
to configure the FPGA via JTAG actually succeeded!?!

Ultimately I need a solution because eventually I probably won't have
access to the config device (it's on a small daughterboard) and I just
don't like not knowing *why* it doesn't work!?!

So any suggestions/insight/wild guesses would be most welcome here too!

I guess I should add that CONF_DONE is being routed to an empty header
(for ASM programming) and also an empty socket.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark, that's very interesting. I have a configuration device on my board, 
but I'm not entirely sure that it's wired correctly. (I laid some traces on 
the board wrong and hand-soldered the parts.)

I'll spend some careful time reviewing this. Thank you for your 
observations.

Oddly, I don't see this mentioned in the cyclone datasheet.

-Nevo

"Mark McDougall" <markm@vl.com.au> wrote in message 
news:457cfcd0$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Nevo wrote:
>
>> I have a board designed around the EP1C6 Cyclone device. The Quartus
>> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able 
>> to
>> initiate programming the device over the JTAG port, but Quartus gives me 
>> an
>> error CONF_DONE failed to go high on device 1.
>
> Interesting that you have these problems...
>
> I have very recently inherited a board which I am using for a very
> different purpose to that for which it was originally intended. The
> board is based on an EP2C35 and has options for both passive and active
> serial configuration, as well as JTAG. The former options require
> configuration devices to be plugged into DIP sockets on the board.
>
> Not needing auto-configuration, I dispatched with the config devices (I
> actually don't *own* any) but was met with "CONF_DONE not going high"
> when attempting to configure via JTAG.
>
> After scratching my head for some time, I eventually tried it with the
> config device plugged in - and it worked!
>
> Now I can't for the life of me understand why this device must be
> present for JTAG programming? There's a pullup on CONF_DONE (10k)and
> nSTATUS (10k).
>
> What's more, at one stage I configured the FPGA then removed the config
> device whilst still powered - and I'm pretty sure a subsequent attempt
> to configure the FPGA via JTAG actually succeeded!?!
>
> Ultimately I need a solution because eventually I probably won't have
> access to the config device (it's on a small daughterboard) and I just
> don't like not knowing *why* it doesn't work!?!
>
> So any suggestions/insight/wild guesses would be most welcome here too!
>
> I guess I should add that CONF_DONE is being routed to an empty header
> (for ASM programming) and also an empty socket.
>
> Regards,
>
> -- 
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266 

Perhaps having the config device in is providing enough of load to clean up 
the signals?  Have you looked at the clock and data lines w/o the config 
device in to see if they're clean.  I believe the standard clock rate is 
10MHz, pretty respectable, and needs to treated appropriately during board 
layout.


"Mark McDougall" <markm@vl.com.au> wrote in message 
news:457cfcd0$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Nevo wrote:
>
>> I have a board designed around the EP1C6 Cyclone device. The Quartus
>> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able 
>> to
>> initiate programming the device over the JTAG port, but Quartus gives me 
>> an
>> error CONF_DONE failed to go high on device 1.
>
> Interesting that you have these problems...
>
> I have very recently inherited a board which I am using for a very
> different purpose to that for which it was originally intended. The
> board is based on an EP2C35 and has options for both passive and active
> serial configuration, as well as JTAG. The former options require
> configuration devices to be plugged into DIP sockets on the board.
>
> Not needing auto-configuration, I dispatched with the config devices (I
> actually don't *own* any) but was met with "CONF_DONE not going high"
> when attempting to configure via JTAG.
>
> After scratching my head for some time, I eventually tried it with the
> config device plugged in - and it worked!
>
> Now I can't for the life of me understand why this device must be
> present for JTAG programming? There's a pullup on CONF_DONE (10k)and
> nSTATUS (10k).
>
> What's more, at one stage I configured the FPGA then removed the config
> device whilst still powered - and I'm pretty sure a subsequent attempt
> to configure the FPGA via JTAG actually succeeded!?!
>
> Ultimately I need a solution because eventually I probably won't have
> access to the config device (it's on a small daughterboard) and I just
> don't like not knowing *why* it doesn't work!?!
>
> So any suggestions/insight/wild guesses would be most welcome here too!
>
> I guess I should add that CONF_DONE is being routed to an empty header
> (for ASM programming) and also an empty socket.
>
> Regards,
>
> -- 
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266 

Rob wrote:

> Perhaps having the config device in is providing enough of load to clean up 
> the signals?  Have you looked at the clock and data lines w/o the config 
> device in to see if they're clean.  I believe the standard clock rate is 
> 10MHz, pretty respectable, and needs to treated appropriately during board 
> layout.

But the JTAG lines don't even go to the config devices!

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Good point!  I had in my mind the enhanced configuration devices, which do 
use the JTAG pins.  Post if you find the answer--I would be interested.


"Mark McDougall" <markm@vl.com.au> wrote in message 
news:457e4d43$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Rob wrote:
>
>> Perhaps having the config device in is providing enough of load to clean 
>> up
>> the signals?  Have you looked at the clock and data lines w/o the config
>> device in to see if they're clean.  I believe the standard clock rate is
>> 10MHz, pretty respectable, and needs to treated appropriately during 
>> board
>> layout.
>
> But the JTAG lines don't even go to the config devices!
>
> Regards,
>
> -- 
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266 

Nevo wrote:
> Mark, that's very interesting. I have a configuration device on my board, 
> but I'm not entirely sure that it's wired correctly. (I laid some traces on 
> the board wrong and hand-soldered the parts.)
> 
> I'll spend some careful time reviewing this. Thank you for your 
> observations.
> 
> Oddly, I don't see this mentioned in the cyclone datasheet.
> 
> -Nevo
> 
> "Mark McDougall" <markm@vl.com.au> wrote in message 
> news:457cfcd0$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
>> Nevo wrote:
>>
>>> I have a board designed around the EP1C6 Cyclone device. The Quartus
>>> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able 
>>> to
>>> initiate programming the device over the JTAG port, but Quartus gives me 
>>> an
>>> error CONF_DONE failed to go high on device 1.
>> Interesting that you have these problems...
>>
>> I have very recently inherited a board which I am using for a very
>> different purpose to that for which it was originally intended. The
>> board is based on an EP2C35 and has options for both passive and active
>> serial configuration, as well as JTAG. The former options require
>> configuration devices to be plugged into DIP sockets on the board.
>>
>> Not needing auto-configuration, I dispatched with the config devices (I
>> actually don't *own* any) but was met with "CONF_DONE not going high"
>> when attempting to configure via JTAG.
>>
>> After scratching my head for some time, I eventually tried it with the
>> config device plugged in - and it worked!
>>
>> Now I can't for the life of me understand why this device must be
>> present for JTAG programming? There's a pullup on CONF_DONE (10k)and
>> nSTATUS (10k).
>>
>> What's more, at one stage I configured the FPGA then removed the config
>> device whilst still powered - and I'm pretty sure a subsequent attempt
>> to configure the FPGA via JTAG actually succeeded!?!
>>
>> Ultimately I need a solution because eventually I probably won't have
>> access to the config device (it's on a small daughterboard) and I just
>> don't like not knowing *why* it doesn't work!?!
>>
>> So any suggestions/insight/wild guesses would be most welcome here too!
>>
>> I guess I should add that CONF_DONE is being routed to an empty header
>> (for ASM programming) and also an empty socket.
>>
>> Regards,
>>
>> -- 
>> Mark McDougall, Engineer
>> Virtual Logic Pty Ltd, <http://www.vl.com.au>
>> 21-25 King St, Rockdale, 2216
>> Ph: +612-9599-3255 Fax: +612-9599-3266 

We don't use configuration devices on any of our FPGAs and have no 
problems configuring them from JTAG or a microcontroller.

Check to make sure that you have pullups on nCONFIG, CONFIG_DONE, and 
nSTATUS. Passive serial configuration devices provide these pullups by 
default, which could be missing on the board. Removing the configuration 
device would remove the pullups, preventing configuration even from JTAG.

Marc