Forums

Synthesis in VHDL vs. Verilog

Started by Chris Carlen January 7, 2004
Greetings:

I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog 
Primer" in order to learn not only Verilog, but how to make sure I can 
model designs in a way that is synthesizable.

What I have just learned is that the synthesis system (such as if I am 
using Xilinx ISE Webpack and it's associated synthesis tools) dictates 
what style must be followed, because one system might be able to 
synthesize model 'A' and not 'B', whereas another system might be able 
to synthesize 'B' and not 'A', even though models 'A' and 'B' are 
functionally equivalent.

Thus, this leads to the question of how to I learn about what modeling 
style will be synthesizable for my particular tools?

The text won't be able to teach me this, since it is just dealing with 
the problem in general.  Obviously this must be in the tooll 
documentation, so I would ask:

Is there good modeling style info in Xilinx tools so that one can learn 
how to make synthesizable models for Xilinx tools reliably?

Finally, how to VHDL and Verilog compare in terms of *inherent* 
synthesizability of models, or does the same problem essentially exist 
for both?

Thanks for input.

Good day!
-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

Chris Carlen <crcarle@bogus.sandia.gov> wrote:
...
: Is there good modeling style info in Xilinx tools so that one can learn 
: how to make synthesizable models for Xilinx tools reliably?

Look on the XILINX site fir xst.pdf amd lib.pdf

...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Chris Carlen <crcarle@bogus.sandia.gov> wrote:
...
: Is there good modeling style info in Xilinx tools so that one can learn 
: how to make synthesizable models for Xilinx tools reliably?

Look on the XILINX site for xst.pdf amd lib.pdf

...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Both VHDL and Verilog were originally developed as simulation languages 
with synthesis coming along later. Both languages have stuff that is 
synthesizable and stuff that is not.

My experience using several VHDL synth tools is that 98% of the stuff 
that is synthesizable under one tool will also be synthesizable under 
another one. Of a much greater variability is how well each tool maps 
the models to the underlying fabric.

IMHO a good generic book about writing synthesizable code will prepare 
you for whatever tool you want to use. Also Xilinx has a guide to 
writing code for synthesis somewhere on their web site that will tell 
you pretty much the same thing. The xilinx docs should also tell you 
what special FPGA constructs like shifters and memory can be inferred 
from your generic code without having to explicitly instantiate them, 
which is good to know.

Jeff

On Wed, 07 Jan 2004 10:21:46 -0800, Chris Carlen wrote:

> Greetings: > > I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog > Primer" in order to learn not only Verilog, but how to make sure I can > model designs in a way that is synthesizable. > > What I have just learned is that the synthesis system (such as if I am > using Xilinx ISE Webpack and it's associated synthesis tools) dictates > what style must be followed, because one system might be able to > synthesize model 'A' and not 'B', whereas another system might be able > to synthesize 'B' and not 'A', even though models 'A' and 'B' are > functionally equivalent. > > Thus, this leads to the question of how to I learn about what modeling > style will be synthesizable for my particular tools? > > The text won't be able to teach me this, since it is just dealing with > the problem in general. Obviously this must be in the tooll > documentation, so I would ask: > > Is there good modeling style info in Xilinx tools so that one can learn > how to make synthesizable models for Xilinx tools reliably? > > Finally, how to VHDL and Verilog compare in terms of *inherent* > synthesizability of models, or does the same problem essentially exist > for both? > > Thanks for input. > > Good day!
I've never run into anything that synthesized with Synplify and not with Precision or vice-versa. Synthesis directives are not standardized so they aren't generally portable although Precision secretly supports a small subset of Synplify directives. XST is a different story, there are lot's of things that didn't work the last time I tried it (I haven't tried the latest rev so it may have improved). Synplify has a good user's guide. If you follow it's rules you won't have any problems with any decent synthesis tool.
"B. Joshua Rosen" <bjrosen@polybus.com> wrote:
> On Wed, 07 Jan 2004 10:21:46 -0800, Chris Carlen wrote: > > > Thus, this leads to the question of how to I learn about what modeling > > style will be synthesizable for my particular tools? > > > > The text won't be able to teach me this, since it is just dealing with > > the problem in general. Obviously this must be in the tooll > > documentation, so I would ask: > > > > Is there good modeling style info in Xilinx tools so that one can learn > > how to make synthesizable models for Xilinx tools reliably? > > > > Finally, how to VHDL and Verilog compare in terms of *inherent* > > synthesizability of models, or does the same problem essentially exist > > for both? > > I've never run into anything that synthesized with Synplify and not with > Precision or vice-versa. Synthesis directives are not standardized so they > aren't generally portable although Precision secretly supports a small > subset of Synplify directives. XST is a different story, there are lot's > of things that didn't work the last time I tried it (I haven't > tried the latest rev so it may have improved). > > Synplify has a good user's guide. If you follow it's rules you won't have > any problems with any decent synthesis tool.
I can't speak for Verilog, but in VHDL I've seen allready problems to migrate from Synopsys to Synplicity and vice versa. Further there are constructs that may synthesise, but fail in our tool for formal verification. I would say, that's the difference between someone just learning the HDL and an experienced HW-Designer. A good book about synthesis will help. Experience or an experienced tutor will might be the other solution. As I bet there's somenone likely starting to bash on VHDL and telling me that will never happen with Verilog, I would bet anything, the same problem will rise when using Systemverilog (which is intended to replace Verilog in the next years). bye Thomas Stanka
Chris Carlen wrote:

> Is there good modeling style info in Xilinx tools so that one can learn > how to make synthesizable models for Xilinx tools reliably?
Use a synchronous template for all processes to minimize synthesis problems.
> Finally, how to VHDL and Verilog compare in terms of *inherent* > synthesizability of models, or does the same problem essentially exist > for both?
They are the same for register level design descriptions. VHDL allows synthesis using more complex data structures and algorithms. -- Mike Treseler
On Fri, 09 Jan 2004 00:15:23 -0800, Thomas Stanka wrote:

> "B. Joshua Rosen" <bjrosen@polybus.com> wrote: >> On Wed, 07 Jan 2004 10:21:46 -0800, Chris Carlen wrote:
> > I would say, that's the difference between someone just learning the > HDL and an experienced HW-Designer. A good book about synthesis will > help. Experience or an experienced tutor will might be the other > solution. > As I bet there's somenone likely starting to bash on VHDL and telling > me that will never happen with Verilog, I would bet anything, the same > problem will rise when using Systemverilog (which is intended to > replace Verilog in the next years). > > bye Thomas Stanka
Verilog is a very simple language so it's easier for the tools guys to get it right. Personnally I stick strictly to Verilog 95, I'm not even considering using any Verilog 2001 constructs in synthesizable code for another year. As for things like System C, that's targeted at testbenches at the moment, I do think that there are any synthesis tools that can handle it.
Both VHDL and Verilog have a synthesis subset.
Some aspects of the synthesis subset are intuitive,
you can't synthesize access types.

Both have a separate standard that govern the
synthesis subset. For VHDL this is 1076.6, for
Verilog it is 1364.1.  If you want to see vendors
support portable coding styles, ask them to support
these standards.  You do need to ask because for
EDA vendors supporting a standard is an investment.
They expect to get something in return - like users
buying their tools.

The VHDL synthesis standard is quite a bit broader
than the Verilog standard, particularly with respect
to registers.  For example, VHDL supports dual
edged registers (separate clocks or rising and
falling edges).  Some of this is representative of VHDL
being more popular for FPGA design (and FPGA's supporting
devices like this).

See also my follow up to the guy who stated:
"Verilog is a very simple language so it's easier for
the tools guys to get it right."


If you are making a saftey critical design, you
would be better off using VHDL.  There are lots of
ways to hang yourself with Verilog (and none of them
give you anything useful at the end of the day).

To sum this up in another way,
"On a bad day coding VHDL, the compiler is going to
abuse you (hence this explains why some hate VHDL),
however, on a bad day coding Verilog, you can embed
bugs that make it essential that you have a great
testbench to find."


Cheers,
Jim Lewis
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



Chris Carlen wrote:
> Greetings: > > I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog > Primer" in order to learn not only Verilog, but how to make sure I can > model designs in a way that is synthesizable. > > What I have just learned is that the synthesis system (such as if I am > using Xilinx ISE Webpack and it's associated synthesis tools) dictates > what style must be followed, because one system might be able to > synthesize model 'A' and not 'B', whereas another system might be able > to synthesize 'B' and not 'A', even though models 'A' and 'B' are > functionally equivalent. > > Thus, this leads to the question of how to I learn about what modeling > style will be synthesizable for my particular tools? > > The text won't be able to teach me this, since it is just dealing with > the problem in general. Obviously this must be in the tooll > documentation, so I would ask: > > Is there good modeling style info in Xilinx tools so that one can learn > how to make synthesizable models for Xilinx tools reliably? > > Finally, how to VHDL and Verilog compare in terms of *inherent* > synthesizability of models, or does the same problem essentially exist > for both? > > Thanks for input. > > Good day!
> Verilog is a very simple language so it's easier for > the tools guys to get it right.
This is an incorrect assumption. Verilog is a less consise language. If you don't follow some adhoc methodology for coding styles, you will not get it right. This fact has been proven time and time again by Verilog experts who have given numerous conference papers how they overcame yet another Verilog issue. And by the way, according to my sources (Cliff C.) this is not a feature that is being fixed in SystemVerilog. VHDL is a very consise language. Code written and simulated in one simulator will behave exactly the same in another simulator. So going back to simple. Verilog is simple to start producing code, however, if you fail to follow the adhoc rules of Verilog coding, it is very easy to get it wrong. Note, this happens to Verilog experts. If you want to get it right with Verilog, you would be best to invest in a Lint tool. In VHDL many lint tool features are built into the language. As a result, you need to learn these rules from either a good book or from a good class. If you fail to learn these rules, getting started will be painful to get by the compiler. However, once you produce working code the likely hood of it being correct is much higher. For example, at DVCon last year, a company who codes their IP in Verilog and translates to VHDL has imposed the strong typing rules of VHDL onto their Verilog designers (via a lint tool). 75% of the time a lint violation resulted in a real bug. It is certainly better to find these issues at compile/lint time rather than spending time simulating an incorrect design. > Personnally I stick strictly to Verilog 95, I'm not even
> considering using any Verilog 2001 constructs in synthesizable code for > another year. As for things like System C, that's targeted at testbenches > at the moment, I do think that there are any synthesis tools that can > handle it. >
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~