Forums

Synthesis in VHDL vs. Verilog

Started by Chris Carlen January 7, 2004
> VHDL is a very consise language. Code written and > simulated in one simulator will behave exactly the > same in another simulator. >
Jim - Concise means succinct, i.e., the opposite of verbose. I've never heard anyone make that claim about VHDL. Maybe you meant precise? Do you have a link to that DVCon paper? I'd like to read it. If not, can you briefly summarize some of the rules this company imposed? Thanks, Robert
On Sun, 11 Jan 2004 15:35:14 -0800, Jim Lewis <Jim@SynthWorks.com>
wrote:

>Verilog is a less consise language. If you don't follow >some adhoc methodology for coding styles, you will not >get it right. This fact has been proven time and time >again by Verilog experts who have given numerous >conference papers how they overcame yet another Verilog >issue. And by the way, according to my sources (Cliff C.) >this is not a feature that is being fixed in SystemVerilog.
I'm hardly an expert in Verilog, yet I have no problems writing code that's easily and correctly synthesized. There are perfectly good reasons for coding in VHDL, perhaps the most compelling of which to me is the ability to more easily include placement information, e.g., RLOCs (I'm going by what people I respect tell me, not personal experience). But writing synthesizeable Verilog is not an issue. I think that Janick Bergeron, the verification guru, came up with the best answer to the which-is-better question. When asked which of the two languages he prefers, he said it's whichever one he isn't currently using. Bob Perlman Cambrian Design Works
On Mon, 12 Jan 2004 04:25:26 GMT, Bob Perlman
<bobsrefusebin@hotmail.com> wrote:

>I'm hardly an expert in Verilog, yet I have no problems writing code >that's easily and correctly synthesized. > >There are perfectly good reasons for coding in VHDL, perhaps the most >compelling of which to me is the ability to more easily include >placement information, e.g., RLOCs (I'm going by what people I >respect tell me, not personal experience). But writing synthesizeable >Verilog is not an issue.
Verilog 2001 supports attributes. However, even in this latest version of the language, it still isn't possible to have an attribute whose value is a string that is a function of e.g. a genvar. Details here: http://groups.google.com/groups?threadm=mB7gb.12033%24dH7.6968%40newssvr25.news.prodigy.com [Sarcasm] Clearly the language committee understands the needs of users.
>I think that Janick Bergeron, the verification guru, came up with the >best answer to the which-is-better question. When asked which of the >two languages he prefers, he said it's whichever one he isn't >currently using.
I dislike both VHDL and Verilog. Neither do what I want, although Verilog is much further away from the level of abstraction at which I wish to work. VHDL with some degree of OO would be nice. I await the results of the VHDL 200x committees. Regards, Allan.
>So going back to simple. Verilog is simple to start >producing code, however, if you fail to follow the >adhoc rules of Verilog coding, it is very easy to >get it wrong. Note, this happens to Verilog experts. >If you want to get it right with Verilog, you would >be best to invest in a Lint tool.
Do such tools exist? Any of them free/cheap? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Bob Perlman wrote:
> On Sun, 11 Jan 2004 15:35:14 -0800, Jim Lewis <Jim@SynthWorks.com> > wrote: > > >>Verilog is a less consise language. If you don't follow >>some adhoc methodology for coding styles, you will not >>get it right. This fact has been proven time and time >>again by Verilog experts who have given numerous >>conference papers how they overcame yet another Verilog >>issue. And by the way, according to my sources (Cliff C.) >>this is not a feature that is being fixed in SystemVerilog. > > > I'm hardly an expert in Verilog, yet I have no problems writing code > that's easily and correctly synthesized. > > There are perfectly good reasons for coding in VHDL, perhaps the most > compelling of which to me is the ability to more easily include > placement information, e.g., RLOCs (I'm going by what people I > respect tell me, not personal experience). But writing synthesizeable > Verilog is not an issue. > > I think that Janick Bergeron, the verification guru, came up with the > best answer to the which-is-better question. When asked which of the > two languages he prefers, he said it's whichever one he isn't > currently using. > > Bob Perlman > Cambrian Design Works
Thanks Bob and everyone else who responded to my inquiry. I'm not going to get into another round of second guessing about my choice to use Verilog. Since I will be using it sporadically for things that are only a little too complicated to do with a schematic easily, I could even design at the gate instantiation level if I wanted to. I doubt I will have too much trouble, and I intend to learn as much as I can about synthesizability in the process of learning the language. Good day! -- ____________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov
On Mon, 12 Jan 2004 16:06:54 +1100, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

>Verilog 2001 supports attributes. However, even in this latest >version of the language, it still isn't possible to have an attribute >whose value is a string that is a function of e.g. a genvar. > >Details here: >http://groups.google.com/groups?threadm=mB7gb.12033%24dH7.6968%40newssvr25.news.prodigy.com > >[Sarcasm] Clearly the language committee understands the needs of >users.
That's a very interesting thread; I missed it the first time around. Thanks for pointing it out. Bob Perlman Cambrian Design Works
Jim Lewis <Jim@SynthWorks.com> writes:

> their IP in Verilog and translates to VHDL has imposed > the strong typing rules of VHDL onto their Verilog
But, there is only one type -- "wire"... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
Robert,

The paper is paper 6.1:
   AVOIDING ANOTHER VERILOG/VHDL WAR:
   GOOD CODING PRACTICES FOR SOFT IP VENDORS
   Dhanendra Jani, Tensilica Inc., Santa Clara, CA
   Alain Raynaud, Tensilica Inc., Santa Clara, CA

   The quoted number came from the presentation and I could
   not find it in the paper.  The paper is copyrighted, so
   I can't send you a copy.  You may be able to find the paper
   on Tensilica's website.  If you went to DVCon or have access
   to a disk, it is paper 6.1.

 > Maybe you meant precise?
Exactly.

My brain just blew a fuse when with the ironic statement:
"Verilog is a very simple language so it's easier for
the tools guys to get it right."

Historically the problem with Verilog was that it
executes differently on different platforms unless
you follow some adhoc coding rules.  How quick we
forget.

VHDL never had race conditions and never will.

Cheers,
Jim



Robert Sefton wrote:

>>VHDL is a very consise language. Code written and >>simulated in one simulator will behave exactly the >>same in another simulator. >> > > > Jim - > > Concise means succinct, i.e., the opposite of verbose. I've never heard > anyone make that claim about VHDL. Maybe you meant precise? > > Do you have a link to that DVCon paper? I'd like to read it. If not, can > you briefly summarize some of the rules this company imposed? > > Thanks, > > Robert > >
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
On Mon, 12 Jan 2004 15:05:11 -0800, Jim Lewis <Jim@SynthWorks.com>
wrote:

>VHDL never had race conditions and never will.
It's actually quite easy to make races in VHDL. Experience indicates that even simple examples may produce different results on different LRM compliant simulators. signal clk1, clk2 : std_logic; signal sig1 : std_logic; ... clk2 <= clk1; -- clk2 lags clk1 by 1 delta process (clk1) ... sig1 <= foo; ... process (clk2) ... bar <= sig1; ... Astute designers will modify their coding standards to disallow clock assignments such as the one above. Jim, when discussing the relative merits of Verilog and VHDL it is important not to make false claims about either language. Regards, Allan.
Allan,
 > It's actually quite easy to make races in VHDL.
I agree this is a clock to data race condition,
however, it is also easy to avoid and easy to
even forget the rule exists.

Are you suggesting that Verilog race conditions
are as simple to solve as this?  :)  After reading
Cliff's papers, I would conclude that it is not
an insignificant issue in Verilog.


 > Experience indicates that even simple examples
 > may produce different results on different
 > LRM compliant simulators.

My read on the LRM and simulation cycle says that
if two simulators execute your example differently,
one of them is not compliant.
Have you seen different results for a delta
cycle situation like this that was not a
simulator bug?


Regards,
Jim

 > Jim, when discussing the relative merits of Verilog
 > and VHDL it is important not to make false claims
 > about either language.
Oops, it was not intentional.
Verilog does have a large, common problem in this area.
With VHDL it is minor enough to easily forget about it.



Allan Herriman wrote:

> On Mon, 12 Jan 2004 15:05:11 -0800, Jim Lewis <Jim@SynthWorks.com> > wrote: > > >>VHDL never had race conditions and never will. > > > It's actually quite easy to make races in VHDL. Experience indicates > that even simple examples may produce different results on different > LRM compliant simulators. > > > signal clk1, clk2 : std_logic; > signal sig1 : std_logic; > > ... > > clk2 <= clk1; -- clk2 lags clk1 by 1 delta > > process (clk1) > ... > sig1 <= foo; > ... > > process (clk2) > ... > bar <= sig1; > ... > > > Astute designers will modify their coding standards to disallow clock > assignments such as the one above. > > Jim, when discussing the relative merits of Verilog and VHDL it is > important not to make false claims about either language. > > Regards, > Allan.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~