3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4

I want to drive a LVPECL_25 input on a bank with VCCO=2.5V with a 3.3V
LVPECL signal.  Xilinx has a nice app note on doing this with a Virtex
ii and a Spartan 3, but I can't find anything concrete about doing it
on a Virtex-4.  Would you agree that it's safe to implement the same
solution on a Virtex-4?

Here's the app note:
http://www.xilinx.com/bvdocs/appnotes/xapp696.pdf
See page 4.

It's just a voltage divider.  Are there any adverse effects to this?

Thanks,
Dale

Dale,

This will work.

Some care is required to keep everything short (try not to create stubs
that cause reflections).  Figure 4 is the DC divider, or Figure 6 is the
AC coupling solution (both will work).  AC coupling may be an issue if
the signals are not balanced (more 0's than 1's or more 1's than 0's).

Works for S3, S3E, S3A, V4 and V5.

Austin
(Xilinx ICDES)

> I want to drive a LVPECL_25 input on a bank with VCCO=2.5V with a 3.3V
> LVPECL signal.  Xilinx has a nice app note on doing this with a Virtex
> ii and a Spartan 3, but I can't find anything concrete about doing it
> on a Virtex-4.  Would you agree that it's safe to implement the same
> solution on a Virtex-4?
> 
> Here's the app note:
> http://www.xilinx.com/bvdocs/appnotes/xapp696.pdf
> See page 4.
> 
> It's just a voltage divider.  Are there any adverse effects to this?
> 
> Thanks,
> Dale
>