I feel it is better to start a new thread, I have compiled my divide oscillator clock by ten module, what do I do now? //////////////////////////////////////////////////////////////////////////// ////// module clkdiv10mod(in, out); input in; output out; reg [3:0] cnt; always @ (in) begin cnt=cnt+1; if (cnt ==9) begin cnt =0; cnt =!cnt; end end endmodule Here is my console output: ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "clkdiv10mod.v" in library work Module <clkdiv10mod> compiled No errors in compilation Analysis of file <"clkdiv10mod.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module <clkdiv10mod> in library <work>. Building hierarchy successfully finished. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module <clkdiv10mod>. Module <clkdiv10mod> is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <clkdiv10mod>. Related source file is "clkdiv10mod.v". WARNING:Xst:647 - Input <in> is never used. WARNING:Xst:1306 - Output <out> is never assigned. Found 4-bit adder for signal <$old_cnt_1>. Summary: inferred 1 Adder/Subtractor(s). Unit <clkdiv10mod> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 4-bit adder : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 4-bit adder : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <clkdiv10mod> ... ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- WARNING:ProjectMgmt - "C:/Xilinx/clkdiv10/clkdiv10mod.ngc" line 0 duplicate design unit: 'Module|clkdiv10mod' Process "Synthesize" completed successfully Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise c:/Xilinx/clkdiv10/clkdiv10.ise -intstyle ise -dd _ngo -i -p xc9500 clkdiv10mod.ngc clkdiv10mod.ngd Reading NGO file 'c:/Xilinx/clkdiv10/clkdiv10mod.ngc' ... Loading design module "c:\Xilinx\clkdiv10/clkdiv10mod.ngc"... WARNING:NgdBuild:578 - Design contains no instances. Checking timing specifications ... Checking Partitions ... Checking expanded design ... Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 1 Writing NGD file "clkdiv10mod.ngd" ... Writing NGDBUILD log file "clkdiv10mod.bld"... NGDBUILD done. Process "Translate" completed successfully Started : "Fit". ERROR:Cpld:1005 - Design 'clkdiv10mod' has no outputs. Process "Fit" failed
Frequency divider ?
Started by ●December 18, 2006
Reply by ●December 18, 20062006-12-18
<222> wrote in message news:45873ba6$1_3@mk-nntp-2.news.uk.tiscali.com...>I feel it is better to start a new thread, I have compiled my > divide oscillator clock by ten module, what do I do now?Get out a simulator and see if it works. Once you've done some of your own work, perhaps ask for some help. KJ
Reply by ●December 18, 20062006-12-18
"KJ" <kkjennings@sbcglobal.net> wrote in message news:s6Hhh.4519$yC5.3050@newssvr27.news.prodigy.net...> > <222> wrote in message news:45873ba6$1_3@mk-nntp-2.news.uk.tiscali.com... > >I feel it is better to start a new thread, I have compiled my > > divide oscillator clock by ten module, what do I do now? > > Get out a simulator and see if it works. Once you've done some of yourown> work, perhaps ask for some help.No, no need to simulate, I am ready for the real thing Please contine (as opposed to 'break')> > KJ > >
Reply by ●December 18, 20062006-12-18
<222> wrote in message news:45874059$1_1@mk-nntp-2.news.uk.tiscali.com...> > "KJ" <kkjennings@sbcglobal.net> wrote in message > news:s6Hhh.4519$yC5.3050@newssvr27.news.prodigy.net... >> >> <222> wrote in message news:45873ba6$1_3@mk-nntp-2.news.uk.tiscali.com... >> >I feel it is better to start a new thread, I have compiled my >> > divide oscillator clock by ten module, what do I do now? >> >> Get out a simulator and see if it works. Once you've done some of your > own >> work, perhaps ask for some help. > > > No, no need to simulate, I am ready for the real thing > Please contine (as opposed to 'break') >You have EVERY reason to simulate.. By trivial inspection I can tell that your design doesn't do anything at all. You could start by pondering on the warning messages out of the HDL Synthesis that 'warn' you that input 'in' is never used and output 'out' is never assigned and try to figure out why that would be (Hint: Input 'in' is never used BECAUSE output 'out' is never assigned and since 'out' is the only output this would imply that there is no need for any inputs). Since no inputs or resources of any kind are needed to implement your code, eventually this leads to the fitting error....once again, perhaps read the error message that says that your module has no outputs. In any case, I'll repeat the suggestion to start to use a simulator and simulate your code. There is not much point in running through the synthesis process until you have functioning code....and you can't say you have functioning code until it works at least in a simulation environment. KJ
Reply by ●December 19, 20062006-12-19
"KJ" <kkjennings@sbcglobal.net> wrote in message news:XRHhh.38396$qO4.9412@newssvr13.news.prodigy.net...> > <222> wrote in message news:45874059$1_1@mk-nntp-2.news.uk.tiscali.com... > > > > "KJ" <kkjennings@sbcglobal.net> wrote in message > > news:s6Hhh.4519$yC5.3050@newssvr27.news.prodigy.net... > >> > >> <222> wrote in messagenews:45873ba6$1_3@mk-nntp-2.news.uk.tiscali.com...> >> >I feel it is better to start a new thread, I have compiled my > >> > divide oscillator clock by ten module, what do I do now? > >> > >> Get out a simulator and see if it works. Once you've done some of your > > own > >> work, perhaps ask for some help. > > > > > > No, no need to simulate, I am ready for the real thing > > Please contine (as opposed to 'break') > > > > You have EVERY reason to simulate.. By trivial inspection I can tell that > your design doesn't do anything at all. You could start by pondering onthe> warning messages out of the HDL Synthesis that 'warn' you that input 'in'is> never used and output 'out' is never assigned and try to figure out whythat Why do you say that my input is never used, what about always @ (in) ?> would be (Hint: Input 'in' is never used BECAUSE output 'out' is never > assigned and since 'out' is the only output this would imply that there is > no need for any inputs). Since no inputs or resources of any kind are > needed to implement your code, eventually this leads to the fitting > error....once again, perhaps read the error message that says that your > module has no outputs.What about out = !out is that not an assignment ?> > In any case, I'll repeat the suggestion to start to use a simulator and > simulate your code. There is not much point in running through the > synthesis process until you have functioning code....and you can't say you > have functioning code until it works at least in a simulation environment.Please explain how to simulate, my device is xc9536 and the software is Xilinx ISE 8.2i Tia.> > KJ > >
Reply by ●December 19, 20062006-12-19
On 2006-12-19, <222> <222> wrote:> Why do you say that my input is never used, what about > > always @ (in) ?If I run your design through leda (a linter for VHDL and Verilog) I get the following two warnings: * Signal cnt is missing in the sensitivity list * An asynchronous feedback loop was detected on cnt. What it boils down to is that if you have an @() statement with only signals in it (no posedge or negedge) the synthesizer will infer combinatorial logic from it. And the synthesizer will not care about the sensitivity list at all basically. (It will handle it like you wrote always @* in Verilog 2001 more or less.) If you want something to synthesize, restrict yourself to always @(*) and always @(posedge clocksignal). If you want an asynchronous reset you can also use something like always @(posedge clocksignal or posedge resetsignal). (Or negedge as appropriate.) Otherwise you will most likely get a design that will not work in the same way as your simulation. /Andreas
Reply by ●December 19, 20062006-12-19
"Andreas Ehliar" <ehliar@isy.liu.se> wrote in message news:em8oe2$2j0$1@news.lysator.liu.se...> On 2006-12-19, <222> <222> wrote: > > Why do you say that my input is never used, what about > > > > always @ (in) ? > > If I run your design through leda (a linter for VHDL and > Verilog) I get the following two warnings: > > * Signal cnt is missing in the sensitivity listWhat is a sensitivity list, please add it as appropriate so that I can recompile the program.> * An asynchronous feedback loop was detected on cnt.Please, can you correct the feedback, I have no idea where this feedback is coming from, thanks.> > What it boils down to is that if you have an @() statement > with only signals in it (no posedge or negedge) the synthesizer > will infer combinatorial logic from it. And the synthesizer will > not care about the sensitivity list at all basically. (It willThere currently is no sensitivity list, hence I assume combinational logic is what we want.> handle it like you wrote always @* in Verilog 2001 more or > less.) > > If you want something to synthesize, restrict yourself to > always @(*) and always @(posedge clocksignal). > > If you want an asynchronous reset you can also use something like > always @(posedge clocksignal or posedge resetsignal). > > (Or negedge as appropriate.) > > Otherwise you will most likely get a design that will not > work in the same way as your simulation. > > > /Andreas
Reply by ●December 19, 20062006-12-19
This thread is getting more amusing the longer it gets. :) Mike <222> wrote in message news:4587ed26$1_1@mk-nntp-2.news.uk.tiscali.com...> > "Andreas Ehliar" <ehliar@isy.liu.se> wrote in message > news:em8oe2$2j0$1@news.lysator.liu.se... >> On 2006-12-19, <222> <222> wrote: >> > Why do you say that my input is never used, what about >> > >> > always @ (in) ? >> >> If I run your design through leda (a linter for VHDL and >> Verilog) I get the following two warnings: >> >> * Signal cnt is missing in the sensitivity list > > What is a sensitivity list, please add it as appropriate so that > I can recompile the program. > > >> * An asynchronous feedback loop was detected on cnt. > > Please, can you correct the feedback, I have no idea where > this feedback is coming from, thanks. > > >> >> What it boils down to is that if you have an @() statement >> with only signals in it (no posedge or negedge) the synthesizer >> will infer combinatorial logic from it. And the synthesizer will >> not care about the sensitivity list at all basically. (It will > > There currently is no sensitivity list, hence I assume combinational > logic is what we want. > > >> handle it like you wrote always @* in Verilog 2001 more or >> less.) >> >> If you want something to synthesize, restrict yourself to >> always @(*) and always @(posedge clocksignal). >> >> If you want an asynchronous reset you can also use something like >> always @(posedge clocksignal or posedge resetsignal). >> >> (Or negedge as appropriate.) >> >> Otherwise you will most likely get a design that will not >> work in the same way as your simulation. >> >> >> /Andreas > >
Reply by ●December 19, 20062006-12-19
"Mike Lewis" <someone@micrsoft.com> wrote in message news:RYmdndDB8vc1gRXYnZ2dnUVZ_uuqnZ2d@magma.ca...> This thread is getting more amusing the longer it gets. :)Does anyone else suspect that '222' is actually a Turing machine configured to teach itself Verilog programming by holding pseudo-natural-language conversations on Usenet? It's certainly neither an engineer nor anyone who's ever going to be one. Will
Reply by ●December 19, 20062006-12-19
Mike Lewis wrote:> This thread is getting more amusing the longer it gets. :) > > Mike >He should start another one...again. <222> Your absolute lack of understanding is astounding. Even after people have given more help than you deserve, you continue to post things that make no sense. "out = !out is that not an assignment ?" Yes, it is. Too bad you are not using it. I dare you to try and draw the hardware you are attempting to make. Becuase what you have so far is awesome. I am incorporating it into my current design. It is basically a neural-computer that posts to forums in search of answers for every single issue for everything in life. Otherwise, I may have to read a manual or book to learn something. always @(anything_i_dont_understand_immediately) post_to_forum = 1'b1; always @(always) //is this a verilog construct...hmmmmmm, I wish. rtfm = 1'b0; Here is how I suggest you code you counter: always @(when_you_should) divide_my_clock_by_10 There has to be some synthesis tool that will infer correctly from here. Oh, and keep making the same signal equal to two different values at the same time. That will always work out for you. Wired-OR is your friend too. Sorry if this is a mean post, but some people aren't cut out for this stuff.
