jtag reset seq

I have a simple doubt about resetting sequence of Tap state machine
One way of resetting TAP FSM is through trst signal. Making trst
1(along with TMS=1 for the time trst transitions from 0 to 1) resets
the state machine and it enter run-test-idle mode.

A other way is by asserting TMS=1 for five TCK.. But am not able to do
it this way.. Any clues where i may be going wrong? What should be the
value on other test signals at this time? Since in my case the TAP
remains in test-logic-reset state

Not sure why you think the tap controller should be in run-test-idle
after reset. It should go to the reset state (well, ie
test-logic-reset).

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/


gomsi wrote:
> I have a simple doubt about resetting sequence of Tap state machine
> One way of resetting TAP FSM is through trst signal. Making trst
> 1(along with TMS=1 for the time trst transitions from 0 to 1) resets
> the state machine and it enter run-test-idle mode.
>
> A other way is by asserting TMS=1 for five TCK.. But am not able to do
> it this way.. Any clues where i may be going wrong? What should be the
> value on other test signals at this time? Since in my case the TAP
> remains in test-logic-reset state

Actually following the normal logic of resetting the TAP using trst, if
after assetion of trst if TMS is low, it will come to run-test-idle
state.It is clearly visible from TAP state machine. It can remain in
test-logic-reset after reset from trst only if TMS is held high..


Jim Wu wrote:
> Not sure why you think the tap controller should be in run-test-idle
> after reset. It should go to the reset state (well, ie
> test-logic-reset).
>
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
>
>
> gomsi wrote:
> > I have a simple doubt about resetting sequence of Tap state machine
> > One way of resetting TAP FSM is through trst signal. Making trst
> > 1(along with TMS=1 for the time trst transitions from 0 to 1) resets
> > the state machine and it enter run-test-idle mode.
> >
> > A other way is by asserting TMS=1 for five TCK.. But am not able to do
> > it this way.. Any clues where i may be going wrong? What should be the
> > value on other test signals at this time? Since in my case the TAP
> > remains in test-logic-reset state

gomsi schrieb:

> Actually following the normal logic of resetting the TAP using trst, if
> after assetion of trst if TMS is low, it will come to run-test-idle
> state.It is clearly visible from TAP state machine. It can remain in
> test-logic-reset after reset from trst only if TMS is held high..
>
>

TAP will not transit to any state except on rising edge of TCK

1) if TRST is implemented then when asserted will go to TLR
2) if TRST is not implemented power up default should be TLR
3) if TRST not asserted or not implemented and TMS=1 during 5 TCK
rising edges then state will be TLR
4) transition to RTI will happen on first rising of TCK when TMS=0 and
TRST not asserted when state was TLR

if your TAP controller does something else it is not IEEE 1149.1
confirm.
.

Antti

Antti wrote:
> TAP will not transit to any state except on rising edge of TCK
I guess you meant "any state other than T-L-R, except...", as TRST is an
asynchronous reset. All other state transitions are of course synchronous
to the rising edge of TCK.

> if your TAP controller does something else it is not IEEE 1149.1 
> confirm. 
Unfortunately, most implementations are not really 1149.1 confirm, in one
way or another. Usually you can work around those problems though.

Regards,

Dominic

thanks for the replies..
But As stated by you TAP is working fine.. Since i just wanted to
bypass any effect of TRST on TAP. I followed two ways to bypass trst:
1. Ties TRST to 1 from zero simulation time and then after the power on
of the design i made TMS = 1 for 5 positive edges of TCK. The TAP
does'nt enter RTI.
2. I tried with TRST to 0 from zero simulation, the same logic as
stated earlier, but with the same results..
In both the cases the state machine remains in TLR state throughout the
simulations, irrespective of any stimulus on TMS or TCK

Anyways if the following sequence if followed
(a)  TRST remains low.
(b) TMS is made one and TCK is applied.
(c) TMS remains 1 for 3 TCK
(d) After 3 TCK, TRST is made 1 and TMS made 0.
(e) This sets the TAP in RTI mode and then it works fine..

I was only thinking the other way round i.e. to bypass TRST to get into
RTI from TLR.. And if suggestions are there for that... please guide


Dominic wrote:
> Antti wrote:
> > TAP will not transit to any state except on rising edge of TCK
> I guess you meant "any state other than T-L-R, except...", as TRST is an
> asynchronous reset. All other state transitions are of course synchronous
> to the rising edge of TCK.
>
> > if your TAP controller does something else it is not IEEE 1149.1
> > confirm.
> Unfortunately, most implementations are not really 1149.1 confirm, in one
> way or another. Usually you can work around those problems though.
> 
> Regards,
> 
> Dominic

gomsi schrieb:

> thanks for the replies..
> But As stated by you TAP is working fine.. Since i just wanted to
> bypass any effect of TRST on TAP. I followed two ways to bypass trst:
> 1. Ties TRST to 1 from zero simulation time and then after the power on
> of the design i made TMS = 1 for 5 positive edges of TCK. The TAP
> does'nt enter RTI.

OF COURSE it does not enter RTI when shift in TMS=1

when you clock 5 times TMS=1 then the TAP enter TLR not RTI !!

Antti

Antti.. so how to make it go into RTI... any suggestions
Antti wrote:
> gomsi schrieb:
>
> > thanks for the replies..
> > But As stated by you TAP is working fine.. Since i just wanted to
> > bypass any effect of TRST on TAP. I followed two ways to bypass trst:
> > 1. Ties TRST to 1 from zero simulation time and then after the power on
> > of the design i made TMS = 1 for 5 positive edges of TCK. The TAP
> > does'nt enter RTI.
>
> OF COURSE it does not enter RTI when shift in TMS=1
>
> when you clock 5 times TMS=1 then the TAP enter TLR not RTI !!
> 
> Antti

gomsi schrieb:

> Antti.. so how to make it go into RTI... any suggestions
> Antti wrote:
> > gomsi schrieb:

from TLR

1) TMS=0
2) apply 1 (one) TCK pulse

state will be RTI 

Antti

one last question...
what should be the state of TRST in this case? tied to low or high

thanks

Antti wrote:
> gomsi schrieb:
>
> > Antti.. so how to make it go into RTI... any suggestions
> > Antti wrote:
> > > gomsi schrieb:
>
> from TLR
>
> 1) TMS=0
> 2) apply 1 (one) TCK pulse
> 
> state will be RTI 
> 
> Antti