Help with xilinx simulation?

Hello all,
I am using xilinx ISE 8.2i , my program is as follows,

entity mod1 is
    Port ( a : in  STD_LOGIC;
           y : out  STD_LOGIC);
end mod1;

architecture Behavioral of mod1 is

begin
 y <= a;

end Behavioral;

I need to simulate this simple thing, I created a Test Bench Waveform, which
creates a simulation. I have a clock signal, a, which has 10 periods 100ns
each,
and an output, y, which is constantly zero. Can anyone explain this ?

What does your testbench stimulus of 'a' look like?  I am guessing it does 
not toggle and is always low.  Try toggling the input stimulus and see how 
'y' responds in the simulation.

-davide

<xx> wrote in message news:458c623c$1_3@mk-nntp-2.news.uk.tiscali.com...
> Hello all,
> I am using xilinx ISE 8.2i , my program is as follows,
>
> entity mod1 is
>    Port ( a : in  STD_LOGIC;
>           y : out  STD_LOGIC);
> end mod1;
>
> architecture Behavioral of mod1 is
>
> begin
> y <= a;
>
> end Behavioral;
>
> I need to simulate this simple thing, I created a Test Bench Waveform, 
> which
> creates a simulation. I have a clock signal, a, which has 10 periods 100ns
> each,
> and an output, y, which is constantly zero. Can anyone explain this ?
>
> 

> What does your testbench stimulus of 'a' look like?  I am guessing it does
> not toggle and is always low.  Try toggling the input stimulus and see how
> 'y' responds in the simulation.

The stimulus is automatically applied by the Test Bench Waveofrm wizard,
it is a clock of 5 periods at 1000ns in total (5 periods). There seems to be
little yellow spikes where the clock positive edges are, I don't know what
these are supposed to be. I am supposed to get a clock on y as my module
simple assign y <=a, this is the problem, in the simulation the result is y
=0,
and there are yellow spikes. It's a .tbw file. Do you want me to post it as
an image?

>
> -davide
>
> <xx> wrote in message news:458c623c$1_3@mk-nntp-2.news.uk.tiscali.com...
> > Hello all,
> > I am using xilinx ISE 8.2i , my program is as follows,
> >
> > entity mod1 is
> >    Port ( a : in  STD_LOGIC;
> >           y : out  STD_LOGIC);
> > end mod1;
> >
> > architecture Behavioral of mod1 is
> >
> > begin
> > y <= a;
> >
> > end Behavioral;
> >
> > I need to simulate this simple thing, I created a Test Bench Waveform,
> > which
> > creates a simulation. I have a clock signal, a, which has 10 periods
100ns
> > each,
> > and an output, y, which is constantly zero. Can anyone explain this ?
> >
> >
>
>

a picture is worth a 1000 words:

http://vhdlblog.blogspot.com/

click on the image to see full size

xx wrote:
> http://vhdlblog.blogspot.com/

I expect the problem is in tb.vhd

    -- Mike Treseler

> The stimulus is automatically applied by the Test Bench Waveofrm wizard,
> it is a clock of 5 periods at 1000ns in total (5 periods). There seems to 
> be
> little yellow spikes where the clock positive edges are, I don't know what
> these are supposed to be.
1. You should probably look up in the Xilinx documentation about what the 
yellow spikes are all about.
2. Take a look at the testbench code that was generated, (maybe post that up 
here for all to see).
3. Maybe there is some problem with your simulator.

I realize that the testbench code that you're using was generated by Mr. 
Wizard, but it should roughly look like the following....in fact maybe try 
copying the code below into your current testbench code file and comment out 
or delete what is there and try simulating.  If the code below works then 
you should look for differences between it and the Mr. Wizard generated 
testbench code (after finding out what yellow spikes are) and try to figure 
out what is going on.

entity tb is
end tb

architecture RTL of tb is
   signal a: std_logic := '0';
   signal y:
begin
    a <= not(a) after 100 ns;
    DUT : entity work.mod1 port map(a => a, y => y);
end RTL;

KJ

Is this your first simulation ever? Perhaps you are not using
the tools properly. You have to save the testbench, make sure that
the test bench is highlighted in the source pane, (the testbench
should be under the mod1), and in the process pane the Simulate
Behavior needs to be clicked. I'm not an 8.2 user yet, so perhaps
there is some other things to watch out for.

Then you should try y<='1'; to see if you can get the signal to
move.

Brad Smallridge
AiVision

p
<xx> wrote in message news:458c623c$1_3@mk-nntp-2.news.uk.tiscali.com...
> Hello all,
> I am using xilinx ISE 8.2i , my program is as follows,
>
> entity mod1 is
>    Port ( a : in  STD_LOGIC;
>           y : out  STD_LOGIC);
> end mod1;
>
> architecture Behavioral of mod1 is
>
> begin
> y <= a;
>
> end Behavioral;
>
> I need to simulate this simple thing, I created a Test Bench Waveform, 
> which
> creates a simulation. I have a clock signal, a, which has 10 periods 100ns
> each,
> and an output, y, which is constantly zero. Can anyone explain this ?
>
> 

> Is this your first simulation ever? Perhaps you are not using
> the tools properly. You have to save the testbench, make sure that

The fact that I am getting a simulation indicates to me that I have
been using the tools correctly. The fact that the simulation is
not working indicate to me that xilinx tools do not work 'out of
the box' (if at all).


> the test bench is highlighted in the source pane, (the testbench
> should be under the mod1), and in the process pane the Simulate
> Behavior needs to be clicked. I'm not an 8.2 user yet, so perhaps
> there is some other things to watch out for.
>
> Then you should try y<='1'; to see if you can get the signal to
> move.

y<='1'; is the same, output is y = 0

> I expect the problem is in tb.vhd

What am I supposed to ask?

> 1. You should probably look up in the Xilinx documentation about what the
> yellow spikes are all about.

These comment were made so that people know what I am looking at.
Reading the manuals will come later, after I know the xilinx tools do
work. After all, what good is it to learn a tool if it doesn't work?

> 2. Take a look at the testbench code that was generated, (maybe post that
up
> here for all to see).

I explained what I did, surely you can duplicate it and see what the
code is ?

> 3. Maybe there is some problem with your simulator.
>
> I realize that the testbench code that you're using was generated by Mr.
> Wizard, but it should roughly look like the following....in fact maybe try
> copying the code below into your current testbench code file and comment
out
> or delete what is there and try simulating.  If the code below works then
> you should look for differences between it and the Mr. Wizard generated
> testbench code (after finding out what yellow spikes are) and try to
figure
> out what is going on.

OK I'll see if I can, but really, I don't want to be debugging for xilinx,
this
is their job. If it doesn't work, I'll wait for their next version.

>
> entity tb is
> end tb
>
> architecture RTL of tb is
>    signal a: std_logic := '0';
>    signal y:
> begin
>     a <= not(a) after 100 ns;
>     DUT : entity work.mod1 port map(a => a, y => y);
> end RTL;
>
> KJ
>
>