Hello Folks,
I'm writting a slave SPI code for my FPGA and very sure that
my master is generating the right SPI but somehow slave is unable to
decode it. I've never used the verilog before so it might be possible
that something is wrong with my code. Please advice.
_________________________________________________________________________
module test_spi(led,MOSI,SS,SCK,clk);
output [7:0] led;
input MOSI, SS, SCK, clk;
wire MOSI;
wire SS;
wire SCK;
wire clk;
reg num = 7;
reg [7:0] temp = 0;
reg SCK_LAST;
reg SCK_NOW;
reg [7:0] led;
always @(posedge clk)
begin
if (!SS)
begin
SCK_LAST = SCK_NOW;
SCK_NOW = SCK;
if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising
edge
begin
if (num < 8) // 8 bits counter
begin
if (!MOSI)
begin
temp = (temp << 1); //1 bit-shift and store it to temp when
receiving "0"
end
else
begin
temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp
when receiving "1"
end
if (num == 0)
begin
led = temp; //output to the LED on the board
num = 10;
end
end
end
num = num - 1;
end
else
begin
num = 7; //reset counter and temp store
temp = 8'b0;
end
end
endmodule
_________________________________________________________________________
Thanks for your time.
SPI slave problem
Started by ●December 29, 2006
Reply by ●December 29, 20062006-12-29
On 2006-12-29, mankin18@gmail.com <mankin18@gmail.com> wrote:> that something is wrong with my code. Please advice. > > reg num = 7;That's almost certainly wrong. I can't vouch for the rest. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/
Reply by ●December 29, 20062006-12-29
On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote:> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > > that something is wrong with my code. Please advice. > > > reg num = 7;That's almost certainly wrong. I can't vouch for the rest. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/Thanks for prompt response! but can you elaborate a bit more?
Reply by ●December 29, 20062006-12-29
mankin18@gmail.com wrote:> > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: >> >> > that something is wrong with my code. Please advice. >> >> > reg num = 7;That's almost certainly wrong. I can't vouch for >> > the rest. >> >> -- >> Ben Jackson AD7GD >> <b...@ben.com>http://www.ben.com/ > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be reg [2:0] num; Best regards, Ben
Reply by ●December 29, 20062006-12-29
On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...@gmail.com> wrote:> manki...@gmail.com wrote: > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > >> > that something is wrong with my code. Please advice. > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > >> > the rest. > > >> -- > >> Ben Jackson AD7GD > >> <b...@ben.com>http://www.ben.com/ > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > reg [2:0] num; > > Best regards, > > Ben- Hide quoted text -- Show quoted text -ben! thanks for clue. Let me try and i'll get back to you as i'm also not a verilog guy;-) Cheers
Reply by ●December 29, 20062006-12-29
On Dec 29, 4:03 pm, manki...@gmail.com wrote:> On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...@gmail.com> wrote: > > > > > > > manki...@gmail.com wrote: > > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > > >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > > >> > that something is wrong with my code. Please advice. > > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > > >> > the rest. > > > >> -- > > >> Ben Jackson AD7GD > > >> <b...@ben.com>http://www.ben.com/ > > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > > reg [2:0] num; > > > Best regards, > > > Ben- Hide quoted text -- Show quoted text -ben! thanks for clue. Let me try and i'll get back to you as i'm also > not a verilog guy;-) > > Cheers- Hide quoted text -- Show quoted text -0ops! and no difference, any idea? --
Reply by ●December 29, 20062006-12-29
Ben Jackson schrieb:>> reg num = 7; > > That's almost certainly wrong.Initial values are ignored during synthesis. -> Create a reset for it! Ralf
Reply by ●December 29, 20062006-12-29
mankin18@gmail.com wrote:> On Dec 29, 4:03 pm, manki...@gmail.com wrote: > > On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...@gmail.com> wrote: > > > > > > > > > > > > > manki...@gmail.com wrote: > > > > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > > > >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > > > > >> > that something is wrong with my code. Please advice. > > > > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > > > >> > the rest. > > > > > >> -- > > > >> Ben Jackson AD7GD > > > >> <b...@ben.com>http://www.ben.com/ > > > > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > > > > reg [2:0] num; > > > > > Best regards, > > > > > Ben- Hide quoted text -- Show quoted text -ben! thanks for clue. Let me try and i'll get back to you as i'm also > > not a verilog guy;-) > > > > Cheers- Hide quoted text -- Show quoted text - > > 0ops! and no difference, any idea? > > > --I haven't checked in detail but move "num = num - 1;" inside the check for SCK rising otherwise it gets decremented for every clockcycle not every SCK cycle. easy spot if you run a simulation ;) -Lasse
Reply by ●December 29, 20062006-12-29
mankin18@gmail.com ha scritto:> Hello Folks, > I'm writting a slave SPI code for my FPGA and very sure that > my master is generating the right SPI but somehow slave is unable to > decode it. I've never used the verilog before so it might be possible > that something is wrong with my code. Please advice. > _________________________________________________________________________ > > module test_spi(led,MOSI,SS,SCK,clk); > > output [7:0] led; > > input MOSI, SS, SCK, clk; > > wire MOSI; > wire SS; > wire SCK; > wire clk; > > reg num = 7; > reg [7:0] temp = 0; > reg SCK_LAST; > reg SCK_NOW; > reg [7:0] led; > > > always @(posedge clk) > > begin > if (!SS) > begin > SCK_LAST = SCK_NOW; > SCK_NOW = SCK; > if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising > edge > begin > if (num < 8) // 8 bits counter > begin > if (!MOSI) > begin > temp = (temp << 1); //1 bit-shift and store it to temp when > receiving "0" > end > else > begin > temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp > when receiving "1" > end > if (num == 0) > begin > led = temp; //output to the LED on the board > num = 10; > end > end > end > num = num - 1; > end > else > begin > num = 7; //reset counter and temp store > temp = 8'b0; > end > > end > > endmodule > > _________________________________________________________________________ > > > Thanks for your time.simply stated you should study Verilog more seriously. Especially topics like blocking and non-blocking assignments and how they are synthesized.
Reply by ●December 30, 20062006-12-30
Ralf Hildebrandt schrieb:> Ben Jackson schrieb: > >>> reg num = 7; >> That's almost certainly wrong. > > Initial values are ignored during synthesis. -> Create a reset for it!Is it true for Verilog? Because at least XST regards initial values in VHDL. I know some years ago, they had been ignored. Bye Tom
