xilinx xc9536?

smount wrote:
> As I said, I did look, but coudn't find
> 
>> If you don't wish to do the work of looking, reading and
>> *understanding*, then our help would be futile anyway.
>>
>> Cheers
>>
>> PeteS
> 
> 

I don't have the datasheets in front of me, but here's a suggestion:

Go to

htttp://www.xilinx.com/

Get to the XL9536 page:

Look for 'application notes'

I am sure there's one on using GCLK

Cheers

PeteS

highZ wrote:
> Which one, there are many datasheets for the 9500 familiy and
> for each specific one. I had a glance at all of them and couldn't
> see all these things. What exactly does 'reset' do in the first
> place, well I will see again if I can find it. Thanks

CPLD data is not the most user friendly, and can give the impression
they do not chase new users.

For Xilinx, look at both the pdf called "XC9500 In-System Programmable
CPLD Family", and also the device data sheet, and you do need to make
the odd leap.

Fig 1 has some overview,  Fig 3, Fig4  have more details.

In fig 1,  GCK is tagged as 3 lines, and Data Sheet PIN map shows GCK1,
GCK2,  GCK3 Fig4 shows how those GCKx lines feed all FF's (Fig 3 calls
them Global Clocks)

Most common Macrocell resource ( CLK, SET, RESET in 9536 case) have the
choice of Global, or Product Term drive. Pin resource also has Global
OE, but called  GTSx in some places, and Global OE in others (see Fig
10)

GSR can map to either SET or RESET, so you can use one gobal signal, to
load one initial pattern into your macrocells  (any mix of 1's and 0's
)

Both Global and PT drive work, but Global is faster and uses less
product terms, so is preferred. Usually you move from using Global only
when they are all committed.

The fitter will choose Global, if given the choice.

Write some code both ways: map CLK to a GCK1 pin, and to a IO pin , and
compare the
Fitter report files.(IIRC Xilinx tag these DesignName.RPT)

You will need to be able to read and understand the fitter report
files, but the compile/fit process is fast, so when faced with
questions like this again, just try it both ways, and
look at the fitter report, to see what the final nett effect is.

-jg

I feel sorry for anyone who does not know what "reset" means, and then
tries to make sense of a halfway-modern CPLD (or FPGA) data sheet.
These data sheets are really written for the knowledgeable engineer;
they are not a basic tutorial. For that there are many textbooks.
Our industry (CPLD and FPGA) is now over 25 years old, and we cannot
let every data sheet go back to square one. That would bore the serious
designers to death.
I am a fan of tutorial information, and I try to sneak explanations in
whenever I see a need. But there is a limit.
Our data sheets will not explain the function of a master-slave
D-flip-flop and its clocking and reset and preset (except saying
whether it is synchronou or asynchronous, and which one overrides the
other.)
The fundamentals are up to schools and universities and libraries to
convey.
Peter Alfke, Xilinx Applications


On Jan 2, 9:23 pm, Jim.Granvi...@gmail.com wrote:
> highZ wrote:
> > Which one, there are many datasheets for the 9500 familiy and
> > for each specific one. I had a glance at all of them and couldn't
> > see all these things. What exactly does 'reset' do in the first
> > place, well I will see again if I can find it. ThanksCPLD data is not the most user friendly, and can give the impression
> they do not chase new users.
>
> For Xilinx, look at both the pdf called "XC9500 In-System Programmable
> CPLD Family", and also the device data sheet, and you do need to make
> the odd leap.
>
> Fig 1 has some overview,  Fig 3, Fig4  have more details.
>
> In fig 1,  GCK is tagged as 3 lines, and Data Sheet PIN map shows GCK1,
> GCK2,  GCK3 Fig4 shows how those GCKx lines feed all FF's (Fig 3 calls
> them Global Clocks)
>
> Most common Macrocell resource ( CLK, SET, RESET in 9536 case) have the
> choice of Global, or Product Term drive. Pin resource also has Global
> OE, but called  GTSx in some places, and Global OE in others (see Fig
> 10)
>
> GSR can map to either SET or RESET, so you can use one gobal signal, to
> load one initial pattern into your macrocells  (any mix of 1's and 0's
> )
>
> Both Global and PT drive work, but Global is faster and uses less
> product terms, so is preferred. Usually you move from using Global only
> when they are all committed.
>
> The fitter will choose Global, if given the choice.
>
> Write some code both ways: map CLK to a GCK1 pin, and to a IO pin , and
> compare the
> Fitter report files.(IIRC Xilinx tag these DesignName.RPT)
>
> You will need to be able to read and understand the fitter report
> files, but the compile/fit process is fast, so when faced with
> questions like this again, just try it both ways, and
> look at the fitter report, to see what the final nett effect is.
> 
> -jg