Problems with 7:1 LVDS Tx using OSEDES (Xilinx)

Started by rao January 5, 2007
Hi,
  I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA)
and trying to use
  the approach as specified in xilinx app note XAPP704 (virtex-4 high
speed single data rate
  LVDS transceiver). The reference design that xilinx provided is for
4:1 (4 parallel data goes
  to 1 channel of LVDS) and it works fine but when I try to change the
parameters to operate
  as 7:1 the design doesn't work (the serial data output doesn't
correspond to parallel data input).

  As the maximum bit per channel for a xilinx OSERDES is 6 I have to
use two OSERDES in
  seires (as master and slave) to make a 7:1 channel.

  I would like to know if any worked on this aspect before and I do
appreciate if any one can
  provide some helpful info to proceed.

Regards
rao

> As the maximum bit per channel for a xilinx OSERDES is 6 > I have to use two OSERDES in > seires (as master and slave) to make a 7:1 channel.
I have been able to get the master/slave OSERDES going at 7:1 rates. It's required for Camera Link interfaces, however, I used the single clock edge rate. No amount of kludging allowed the double edge rate. Perhaps the VHDL code below will give you some clues: Brad Smallridge AiVision signal shift1 : std_logic; signal shift2 : std_logic; begin OSERDES_master : OSERDES generic map ( DATA_RATE_OQ => "SDR", -- Specify data rate to "DDR" or "SDR" DATA_RATE_TQ => "BUF", -- Specify data rate to "DDR", "SDR", or "BUF" DATA_WIDTH => 7, -- DDR: 4,6,8,10 SDR BUF: 2,3,4,5,6,7, or 8 INIT_OQ => '0', -- INIT for Q1 register - '1' or '0' INIT_TQ => '0', -- INIT for Q2 register - '1' or '0' SERDES_MODE => "MASTER", -- Set SERDES mode to "MASTER" or "SLAVE" SRVAL_OQ => '0', -- Define Q1 output value upon SR assertion - '1' or '0' SRVAL_TQ => '0', -- Define Q1 output value upon SR assertion - '1' or '0' TRISTATE_WIDTH => 1) -- Specify parallel to serial converter width -- When DATA_RATE_TQ = DDR: 2 or 4 -- When DATA_RATE_TQ = SDR or BUF: 1 " port map ( OQ => q, -- 1-bit output SHIFTOUT1 => open, -- 1-bit output SHIFTOUT2 => open, -- 1-bit output TQ => open, -- 1-bit output CLK => clk, -- 1-bit input CLKDIV => clkdiv, -- 1-bit input D1 => data(0), -- 1-bit input D2 => data(1), -- 1-bit input D3 => data(2), -- 1-bit input D4 => data(3), -- 1-bit input D5 => data(4), -- 1-bit input D6 => data(5), -- 1-bit input OCE => '1', -- 1-bit input REV => '0', -- 1-bit input SHIFTIN1 => shift1, -- 1-bit input SHIFTIN2 => shift2, -- 1-bit input SR => '0', -- 1-bit input T1 => '0', -- 1-bit input T2 => '0', -- 1-bit input T3 => '0', -- 1-bit input T4 => '0', -- 1-bit input TCE => '0' ); -- 1-bit input OSERDES_slave : OSERDES generic map ( DATA_RATE_OQ => "SDR", -- Specify data rate to "DDR" or "SDR" DATA_RATE_TQ => "BUF", -- Specify data rate to "DDR", "SDR", or "BUF" DATA_WIDTH => 7, -- DDR: 4,6,8,10 SDR BUF: 2,3,4,5,6,7, or 8 INIT_OQ => '0', -- INIT for Q1 register - '1' or '0' INIT_TQ => '0', -- INIT for Q2 register - '1' or '0' SERDES_MODE => "SLAVE", -- Set SERDES mode to "MASTER" or "SLAVE" SRVAL_OQ => '0', -- Define Q1 output value upon SR assertion - '1' or '0' SRVAL_TQ => '0', -- Define Q1 output value upon SR assertion - '1' or '0' TRISTATE_WIDTH => 1) -- Specify parallel to serial converter width -- When DATA_RATE_TQ = DDR: 2 or 4 -- When DATA_RATE_TQ = SDR or BUF: 1 " port map ( OQ => open, -- 1-bit output SHIFTOUT1 => shift1, -- 1-bit output SHIFTOUT2 => shift2, -- 1-bit output TQ => open, -- 1-bit output CLK => clk, -- 1-bit input CLKDIV => clkdiv, -- 1-bit input D1 => '0', -- 1-bit input D2 => '0', -- 1-bit input D3 => data(6), -- 1-bit input D4 => '1', -- 1-bit input D5 => '1', -- 1-bit input D6 => '1', -- 1-bit input OCE => '1', -- 1-bit input REV => '0', -- 1-bit input SHIFTIN1 => '0', -- 1-bit input SHIFTIN2 => '0', -- 1-bit input SR => '0', -- 1-bit input T1 => '0', -- 1-bit input T2 => '0', -- 1-bit input T3 => '0', -- 1-bit input T4 => '0', -- 1-bit input TCE => '0' ); -- 1-bit input
Hi
  Thank you for your info.

  My design is in verilog and almost simular as you have shown
  ( except for the slave OSERDES my connections are

  >       D1 => open,              -- 1-bit input
  >       D2 => open,              -- 1-bit input
  >       D3 => data(6),           -- 1-bit input
  >       D4 => open,              -- 1-bit input
  >       D5 => open,              -- 1-bit input
  >       D6 => open,              -- 1-bit input    ).

  I tried your approach of 0 for D1 and D2, 1 for D4, D5 and D6 for
Slave.

  But I couldn't verify the serial Data of the channel w.r.to the
parallel data input to the
  channel.

  Suppose the parallel data is [ABDCEFG] then in next clkdiv cycle the
channel data
  output should be A-B-C-D-E-F-G per clk. I could n't verify the
process.

  // Master
      OSERDES TX_DAT_OUT_00  (.OQ(PREDATOUT[0]), .SHIFTOUT1(),
.SHIFTOUT2(),        .TQ(), .CLK(TXCLK), .CLKDIV(TXCLKDIV), .D1(DI[0]),
 .D2(DI[1]),  .D3(DI[2]),  .D4(DI[3]),  .D5(DI[4]),  .D6(DI[5]),
.OCE(OCE), .REV(1'b0), .SHIFTIN1(S2M1[0]), .SHIFTIN2(S2M2[0]),
.SR(ORST), .T1(), .T2(), .T3(), .T4(), .TCE());

  // Slave
      OSERDES TX_DAT_OUT_00S (.OQ(),             .SHIFTOUT1(S2M1[0]),
.SHIFTOUT2(S2M2[0]), .TQ(), .CLK(TXCLK), .CLKDIV(TXCLKDIV), .D1(1'b0),
 .D2(1'b0),   .D3(DI[6]),  .D4(1'b1),   .D5(1'b1),   .D6(1'b1),
.OCE(OCE), .REV(1'b0), .SHIFTIN1(),        .SHIFTIN2(),
.SR(ORST), .T1(), .T2(), .T3(), .T4(), .TCE());

Regards
rao

Brad Smallridge wrote:
> > As the maximum bit per channel for a xilinx OSERDES is 6 > > I have to use two OSERDES in > > seires (as master and slave) to make a 7:1 channel. > > I have been able to get the master/slave OSERDES going at 7:1 rates. > It's required for Camera Link interfaces, however, I used the single > clock edge rate. No amount of kludging allowed the double edge rate. > > Perhaps the VHDL code below will give you some clues: > > Brad Smallridge > AiVision > > > signal shift1 : std_logic; > signal shift2 : std_logic; > > begin > > OSERDES_master : OSERDES > generic map ( > DATA_RATE_OQ => "SDR", -- Specify data rate to "DDR" or "SDR" > DATA_RATE_TQ => "BUF", -- Specify data rate to "DDR", "SDR", or > "BUF" > DATA_WIDTH => 7, -- DDR: 4,6,8,10 SDR BUF: 2,3,4,5,6,7, or 8 > INIT_OQ => '0', -- INIT for Q1 register - '1' or '0' > INIT_TQ => '0', -- INIT for Q2 register - '1' or '0' > SERDES_MODE => "MASTER", -- Set SERDES mode to "MASTER" or "SLAVE" > SRVAL_OQ => '0', -- Define Q1 output value upon SR assertion - > '1' or '0' > SRVAL_TQ => '0', -- Define Q1 output value upon SR assertion - > '1' or '0' > TRISTATE_WIDTH => 1) -- Specify parallel to serial converter width > -- When DATA_RATE_TQ = DDR: 2 or 4 > -- When DATA_RATE_TQ = SDR or BUF: 1 " > port map ( > OQ => q, -- 1-bit output > SHIFTOUT1 => open, -- 1-bit output > SHIFTOUT2 => open, -- 1-bit output > TQ => open, -- 1-bit output > CLK => clk, -- 1-bit input > CLKDIV => clkdiv, -- 1-bit input > D1 => data(0), -- 1-bit input > D2 => data(1), -- 1-bit input > D3 => data(2), -- 1-bit input > D4 => data(3), -- 1-bit input > D5 => data(4), -- 1-bit input > D6 => data(5), -- 1-bit input > OCE => '1', -- 1-bit input > REV => '0', -- 1-bit input > SHIFTIN1 => shift1, -- 1-bit input > SHIFTIN2 => shift2, -- 1-bit input > SR => '0', -- 1-bit input > T1 => '0', -- 1-bit input > T2 => '0', -- 1-bit input > T3 => '0', -- 1-bit input > T4 => '0', -- 1-bit input > TCE => '0' ); -- 1-bit input > > OSERDES_slave : OSERDES > generic map ( > DATA_RATE_OQ => "SDR", -- Specify data rate to "DDR" or "SDR" > DATA_RATE_TQ => "BUF", -- Specify data rate to "DDR", "SDR", or > "BUF" > DATA_WIDTH => 7, -- DDR: 4,6,8,10 SDR BUF: 2,3,4,5,6,7, or 8 > INIT_OQ => '0', -- INIT for Q1 register - '1' or '0' > INIT_TQ => '0', -- INIT for Q2 register - '1' or '0' > SERDES_MODE => "SLAVE", -- Set SERDES mode to "MASTER" or "SLAVE" > SRVAL_OQ => '0', -- Define Q1 output value upon SR assertion - > '1' or '0' > SRVAL_TQ => '0', -- Define Q1 output value upon SR assertion - > '1' or '0' > TRISTATE_WIDTH => 1) -- Specify parallel to serial converter width > -- When DATA_RATE_TQ = DDR: 2 or 4 > -- When DATA_RATE_TQ = SDR or BUF: 1 " > port map ( > OQ => open, -- 1-bit output > SHIFTOUT1 => shift1, -- 1-bit output > SHIFTOUT2 => shift2, -- 1-bit output > TQ => open, -- 1-bit output > CLK => clk, -- 1-bit input > CLKDIV => clkdiv, -- 1-bit input > D1 => '0', -- 1-bit input > D2 => '0', -- 1-bit input > D3 => data(6), -- 1-bit input > D4 => '1', -- 1-bit input > D5 => '1', -- 1-bit input > D6 => '1', -- 1-bit input > OCE => '1', -- 1-bit input > REV => '0', -- 1-bit input > SHIFTIN1 => '0', -- 1-bit input > SHIFTIN2 => '0', -- 1-bit input > SR => '0', -- 1-bit input > T1 => '0', -- 1-bit input > T2 => '0', -- 1-bit input > T3 => '0', -- 1-bit input > T4 => '0', -- 1-bit input > TCE => '0' ); -- 1-bit input
rao wrote:
> Hi, > I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA) > and trying to use > the approach as specified in xilinx app note XAPP704 (virtex-4 high > speed single data rate > LVDS transceiver). The reference design that xilinx provided is for > 4:1 (4 parallel data goes > to 1 channel of LVDS) and it works fine but when I try to change the > parameters to operate > as 7:1 the design doesn't work (the serial data output doesn't > correspond to parallel data input). > > As the maximum bit per channel for a xilinx OSERDES is 6 I have to > use two OSERDES in > seires (as master and slave) to make a 7:1 channel. > > I would like to know if any worked on this aspect before and I do > appreciate if any one can > provide some helpful info to proceed. > > Regards > rao >
why not use <http://direct.xilinx.com/bvdocs/appnotes/xapp265.pdf>?