Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use inertial delays, so if you have an assignment such as this: assign #4 sig_out = sig_in; then any pulse on sig_in that is less than 4ns will get swallowed. Modeling transport delays prevents this from happening. Modelsim claims to model transport delays using the +transport_int_delay option for vsim, but this just doesn't seems to work. -Kevin
Transport Delays in Modelsim
Started by ●January 10, 2007
Reply by ●January 11, 20072007-01-11
On Wed, 10 Jan 2007 18:41:44 -0700, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:>Has anyone ever been able to get Modelsim to model transport delays in >Verilog? Verilog simulators, by default, use inertial delays, so if you >have an assignment such as this: > >assign #4 sig_out = sig_in; > >then any pulse on sig_in that is less than 4ns will get swallowed. >Modeling transport delays prevents this from happening. Modelsim claims >to model transport delays using the +transport_int_delay option for >vsim, but this just doesn't seems to work.I think you'll find that this option applies only to interconnect delays that have been backannotated from an SDF file. The Verilog language defines continuous driver delays and net delays to be inertial, and I was under the impression that simulators aren't supposed to disobey that. If you want transport delay in your own Verilog model, use intra-assignment nonblocking delays - try tnis... always @(sig_in) sig_out <= #4 sig_in; (Of course, sig_out needs to be a variable now, not a net.) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●January 11, 20072007-01-11
Jonathan Bromley wrote:> On Wed, 10 Jan 2007 18:41:44 -0700, Kevin Neilson > <kevin_neilson@removethiscomcast.net> wrote: > >> Has anyone ever been able to get Modelsim to model transport delays in >> Verilog? Verilog simulators, by default, use inertial delays, so if you >> have an assignment such as this: >> >> assign #4 sig_out = sig_in; >> >> then any pulse on sig_in that is less than 4ns will get swallowed. >> Modeling transport delays prevents this from happening. Modelsim claims >> to model transport delays using the +transport_int_delay option for >> vsim, but this just doesn't seems to work. > > I think you'll find that this option applies only to interconnect > delays that have been backannotated from an SDF file. The Verilog > language defines continuous driver delays and net delays to be > inertial, and I was under the impression that simulators aren't > supposed to disobey that. > > If you want transport delay in your own Verilog model, use > intra-assignment nonblocking delays - try tnis... > > always @(sig_in) sig_out <= #4 sig_in; > > (Of course, sig_out needs to be a variable now, not a net.)That is wonderful. It totally works. I wish I'd known this before. My Palnitkar book makes no reference to this (unsurprisingly) that I can see though I did find a reference in a book by Bhasker. I would like to be able to adjust the delay on-the-fly, in order to model pad/trace delays that change over time, but I don't think that's possible. I suppose maybe I could get a switchable delay doing something like this: always@(sig_in, dly_sel) sig_out <= dly_sel ? #4 sig_in : #5 sig_in; -Kevin
Reply by ●January 11, 20072007-01-11
On Thu, 11 Jan 2007 12:04:50 -0700, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote: [Jonathan]>> If you want transport delay in your own Verilog model, use >> intra-assignment nonblocking delays - try tnis... >> always @(sig_in) sig_out <= #4 sig_in;>That is wonderful. It totally works. I wish I'd known this before.Lots of people say that when we tell them :-) It can do other magic too. The #N transport delay can be replaced with an event control: sig_out <= @(posedge clk) sig_in; in other words, evaluate sig_in right now, and schedule it for assignment to sig_out on the next posedge; and, even more fun, sig_out <= repeat (4) @(posedge clk) sig_in; which makes a very efficient, very compact model of a 4-stage pipeline delay. Note that the assignment is nonblocking so therefore the statement itself executes in zero time - execution proceeds immediately - even though the assignment takes place some considerable time later.> I would like to >be able to adjust the delay on-the-fly, in order to model pad/trace >delays that change over time, but I don't think that's possible.It's panto time... Oh yes it is!!!! The numeric value in the delay expression is evaluated each time the statement executes; it can be any run-time expression, unlike the delay in a continuous assign which must be an elaboration-time constant. The only thing to note is that any expression needs to be enclosed in parentheses. So... sig_out <= #(base_delay + fudge_factor * temperature) sig_in; Take care, though. This means that later assignments can overtake earlier assignments, if the time delay is sufficiently different: consider this... initial begin S <= #10 expr1; // will update S at time=10 #5 // delay until time=5 S <= #2 expr2; // will update S at time=7 so you get the somewhat counterintuitive result that S takes on the value expr2 at time 7, and then expr1 at time 10. There's one piece of really bad news about this, though. I am not aware of *any* reliable way, in Verilog, of revoking a future nonblocking assignment once you've committed it. Disabling the code block that did the assignment *may* revoke its pending nonblocking assignments - some simulators do that - but it's explicitly left undefined in the LRM. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●January 12, 20072007-01-12
Jonathan Bromley wrote:> On Thu, 11 Jan 2007 12:04:50 -0700, Kevin Neilson > <kevin_neilson@removethiscomcast.net> wrote: > > [Jonathan] >>> If you want transport delay in your own Verilog model, use >>> intra-assignment nonblocking delays - try tnis... >>> always @(sig_in) sig_out <= #4 sig_in; > >> That is wonderful. It totally works. I wish I'd known this before. > > Lots of people say that when we tell them :-) > > It can do other magic too. The #N transport delay can be replaced > with an event control: > > sig_out <= @(posedge clk) sig_in; > > in other words, evaluate sig_in right now, and schedule it for > assignment to sig_out on the next posedge; and, even more > fun, > > sig_out <= repeat (4) @(posedge clk) sig_in; > > which makes a very efficient, very compact model of a > 4-stage pipeline delay. Note that the assignment is nonblocking > so therefore the statement itself executes in zero time - execution > proceeds immediately - even though the assignment takes place > some considerable time later. > >> I would like to >> be able to adjust the delay on-the-fly, in order to model pad/trace >> delays that change over time, but I don't think that's possible. > > It's panto time... Oh yes it is!!!! > > The numeric value in the delay expression is evaluated each time the > statement executes; it can be any run-time expression, unlike the > delay in a continuous assign which must be an elaboration-time > constant. The only thing to note is that any expression needs to > be enclosed in parentheses. So... > > sig_out <= #(base_delay + fudge_factor * temperature) sig_in; > > Take care, though. This means that later assignments can overtake > earlier assignments, if the time delay is sufficiently different: > consider this... > > initial begin > S <= #10 expr1; // will update S at time=10 > #5 // delay until time=5 > S <= #2 expr2; // will update S at time=7 > > so you get the somewhat counterintuitive result that S takes on > the value expr2 at time 7, and then expr1 at time 10. > > There's one piece of really bad news about this, though. > I am not aware of *any* reliable way, in Verilog, of revoking > a future nonblocking assignment once you've committed it. > Disabling the code block that did the assignment *may* > revoke its pending nonblocking assignments - some simulators > do that - but it's explicitly left undefined in the LRM.This is great stuff. I replaced all of my adjustable delay lines, which consisted of long shift registers clocked by a 10GHz clock so I could achive 100ps resolution. This was slowing down the simulation drastically. I guess it is panto time--whatever that might be. -Kevin
Reply by ●January 12, 20072007-01-12
On Fri, 12 Jan 2007 10:35:09 -0700, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:>Jonathan Bromley wrote: >> It's panto time... Oh yes it is!!!!> I guess it is panto time--whatever that might be.Sorry, I should have taken note of your timezone. Someone else please explain :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●January 15, 20072007-01-15
On Fri, 12 Jan 2007 22:27:16 +0000, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:>On Fri, 12 Jan 2007 10:35:09 -0700, Kevin Neilson ><kevin_neilson@removethiscomcast.net> wrote: > >>Jonathan Bromley wrote: >>> It's panto time... Oh yes it is!!!! > >> I guess it is panto time--whatever that might be. > >Sorry, I should have taken note of your timezone. > >Someone else please explain :-)Perhaps this will help.... http://www.shapes.demon.co.uk/photos/Costumes/Panto/tennisboys.jpg Or maybe not! - Brian
