Hi, I was currently using picoblaze with RS-232 with the FPGA running at 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the information I hve gathered, to attain a baud rate of 115200, I would need a clock frequency of 115200 * 16 = 1843200 Hz or something close to that. In the picobalze hdl file, there is a counter that counts 27 cycle at 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work but I keep getting garbage on the terminal program on the computer. I have tried 32 cycles as well as 34 cycles without any luck. I was wondering if anybody has tried this before and can shed some light on the matter. Thanks a lot, Amish
picoblaze RS-232 using 62.5 MHz
Started by ●January 11, 2007
Reply by ●January 11, 20072007-01-11
UARTS are good for a bit of a frequency mismatch but going from .47% error to 2.75% error appears to be too much for your system to handle. Consider dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be important that 1838235 Hz is less than 1843200 Hz but that it's much closer than 1893939 Hz. "axr0284" <axr0284@yahoo.com> wrote in message news:1168533692.658912.327530@i56g2000hsf.googlegroups.com...> Hi, > I was currently using picoblaze with RS-232 with the FPGA running at > 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the > information I hve gathered, to attain a baud rate of 115200, I would > need a clock frequency of 115200 * 16 = 1843200 Hz or something close > to that. > > In the picobalze hdl file, there is a counter that counts 27 cycle at > 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. > So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work > but I keep getting garbage on the terminal program on the computer. I > have tried 32 cycles as well as 34 cycles without any luck. > > I was wondering if anybody has tried this before and can shed some > light on the matter. Thanks a lot, > Amish
Reply by ●January 11, 20072007-01-11
I have tried that and I still get garbage. This is weird. I am wondering if the rest of the UART has something to do with this. Maybe additional changes need to be made. Amish John_H wrote:> UARTS are good for a bit of a frequency mismatch but going from .47% error > to 2.75% error appears to be too much for your system to handle. Consider > dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be > important that 1838235 Hz is less than 1843200 Hz but that it's much closer > than 1893939 Hz. > > > "axr0284" <axr0284@yahoo.com> wrote in message > news:1168533692.658912.327530@i56g2000hsf.googlegroups.com... > > Hi, > > I was currently using picoblaze with RS-232 with the FPGA running at > > 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the > > information I hve gathered, to attain a baud rate of 115200, I would > > need a clock frequency of 115200 * 16 = 1843200 Hz or something close > > to that. > > > > In the picobalze hdl file, there is a counter that counts 27 cycle at > > 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. > > So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work > > but I keep getting garbage on the terminal program on the computer. I > > have tried 32 cycles as well as 34 cycles without any luck. > > > > I was wondering if anybody has tried this before and can shed some > > light on the matter. Thanks a lot, > > Amish
Reply by ●January 11, 20072007-01-11
I think the issue might be in my code. I'll have to debug it. Amish axr0284 wrote:> I have tried that and I still get garbage. This is weird. I am > wondering if the rest of the UART has something to do with this. Maybe > additional changes need to be made. > Amish > > John_H wrote: > > UARTS are good for a bit of a frequency mismatch but going from .47% error > > to 2.75% error appears to be too much for your system to handle. Consider > > dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be > > important that 1838235 Hz is less than 1843200 Hz but that it's much closer > > than 1893939 Hz. > > > > > > "axr0284" <axr0284@yahoo.com> wrote in message > > news:1168533692.658912.327530@i56g2000hsf.googlegroups.com... > > > Hi, > > > I was currently using picoblaze with RS-232 with the FPGA running at > > > 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the > > > information I hve gathered, to attain a baud rate of 115200, I would > > > need a clock frequency of 115200 * 16 = 1843200 Hz or something close > > > to that. > > > > > > In the picobalze hdl file, there is a counter that counts 27 cycle at > > > 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. > > > So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work > > > but I keep getting garbage on the terminal program on the computer. I > > > have tried 32 cycles as well as 34 cycles without any luck. > > > > > > I was wondering if anybody has tried this before and can shed some > > > light on the matter. Thanks a lot, > > > Amish
Reply by ●January 11, 20072007-01-11
axr0284 wrote:> I think the issue might be in my code. I'll have to debug it. > AmishYou could try an intermediate freq, just in case your total system has hit a speed ceiling :) Also, check the bit timing with a scope to confirm you have the numbers right. Some of the better UARTS support fractional baud define, where they do not always use 16 clks per bit, but can rate-multiply between 15 or 16, over the Rx bits. That gives you more Xtal freedom, and you can get closer to the precise baud rate, or higher baudrates. -jg
Reply by ●January 12, 20072007-01-12
Hi, I have used a similar approach with Ken Chapman's UARTs, where I wanted to run at 115200 baud with a 25 MHz reference clock. This particular combination has significant mismatch with an integer enable count, so I did this: always @(posedge clk) begin if (en_16_x_startover) en_16_x_cntr <= 0; else en_16_x_cntr <= en_16_x_cntr + 1; end assign en_16_x_startover = (en_16_x_cntr == 26); assign en_16_x_baud = (en_16_x_cntr == 26) || (en_16_x_cntr == 13); It's always 16 enables per bit, but the enables come every 14, 13, 14, 13... cycles. That was good enough to solve my problem. Eric "-jg" <Jim.Granville@gmail.com> wrote in message news:1168571655.100170.198640@s34g2000cwa.googlegroups.com...> > Some of the better UARTS support fractional baud define, where > they do not always use 16 clks per bit, but can rate-multiply > between 15 or 16, over the Rx bits. That gives you more Xtal > freedom, and you can get closer to the precise baud rate, > or higher baudrates. > > -jg