On Sun, 14 Jan 2007 14:26:57 -0000, "Icky Thwacket" <it@it.it> wrote:>Cross coupled nand set-resets work fine for both Altera FPGA and CPLD's.<loud ringing of alarm bells> Indeed they do; but WHERE are you intending to use one of them? If the set and reset signals you're feeding into them are synchronous (i.e. they are flip-flop outputs) then it makes at least as much sense to implement the SR in a synchronous style. No need for that combinational feedback loop, which will cause (at the very least) warning messages from the timing analyzer. If the set and reset signals are asynchronous, then they may suffer decoding glitches that could give undesirable tripping of your S-R latch if you're unlucky (and, as we all know, your luck generally runs out about two days after you've shipped the product to the most important customer). So you probably need to resynchronise those signals anyway, which means that you could just as easily have used a fully synchronous S-R implementation. So... in almost any realistic situation, the cross-coupled SR latch is either unnecessary or undesirable. It is an example of an asynchronous state machine - admittedly a fairly simple example, and one that's relatively easy to get right - and, like all asynchronous state machines, it requires special techniques to use it properly and to avoid tools making unacceptable optimisations to it. Flame away, I'm sure there are some interesting contrary points of view! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Will FPGAs suit my need?
Started by ●January 13, 2007
Reply by ●January 14, 20072007-01-14
Reply by ●January 14, 20072007-01-14
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:fkgkq2tq92j1ge7rtrj877laehcru2vp9g@4ax.com...> On Sun, 14 Jan 2007 14:26:57 -0000, "Icky Thwacket" > <it@it.it> wrote: > >>Cross coupled nand set-resets work fine for both Altera FPGA and CPLD's. > > <loud ringing of alarm bells> > > Indeed they do; but WHERE are you intending to use one of them? > > If the set and reset signals you're feeding into them are synchronous > (i.e. they are flip-flop outputs) then it makes at least as much > sense to implement the SR in a synchronous style. No need for > that combinational feedback loop, which will cause (at the very least) > warning messages from the timing analyzer. > > If the set and reset signals are asynchronous, then they may > suffer decoding glitches that could give undesirable tripping of > your S-R latch if you're unlucky (and, as we all know, your luck > generally runs out about two days after you've shipped the > product to the most important customer). So you probably > need to resynchronise those signals anyway, which means that > you could just as easily have used a fully synchronous S-R > implementation. > > So... in almost any realistic situation, the cross-coupled SR latch > is either unnecessary or undesirable. It is an example of an > asynchronous state machine - admittedly a fairly simple example, > and one that's relatively easy to get right - and, like all > asynchronous state machines, it requires special techniques > to use it properly and to avoid tools making unacceptable > optimisations to it. > > Flame away, I'm sure there are some interesting contrary > points of view!Streuth! Actually the only place I WOULD use it is for an asynchronous front end interface to a switch, i.e. used as a PROPER switch debouncer with a SPCO switch. I was using it as an illustration! Icky
Reply by ●January 14, 20072007-01-14
NickHolby@googlemail.com wrote:>Nico Coesel wrote: >> This is a dangerous advice. 7400 logic is often used in an >> asynchronous way. Building a flip-flip out of NOR/NAND gates will work >> with 7400 series logic, but in an FPGA it most probably won't. >> > >Does that still stand with CPLDs?It depends on the architecture. CPLD are usually based on an output/flip-flop element preceeded by a 'sum of products' element (larger CPLDs use muxes/switch matrices to get some routing flexibilty). Because the timing to the output is well defined, it can be used as an input to a 'sum of products' element to create an asynchronous latch. An FPGA usually consists of small look-up tables to contain the logic. Each look-up table adds delay. If you have a bunch of logic around a nand/nor based flip-flop, the synthesizer will spread the logic over several look-up tables. The order and timing depends on how the optimizer and router place the logic. It may be that the reset or set conditions don't last long enough to achieve a stable output which may cause all kinds of weird effects (oscillating, not working, sometimes working) and each time you route an FPGA, the placement of the logic is different so the outcome of asynchronous logic may be different. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl
Reply by ●January 15, 20072007-01-15
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:fkgkq2tq92j1ge7rtrj877laehcru2vp9g@4ax.com...> On Sun, 14 Jan 2007 14:26:57 -0000, "Icky Thwacket" > <it@it.it> wrote: > > > So... in almost any realistic situation, the cross-coupled SR latch > is either unnecessary or undesirable. It is an example of an > asynchronous state machine - admittedly a fairly simple example, > and one that's relatively easy to get right - and, like all > asynchronous state machines, it requires special techniques > to use it properly and to avoid tools making unacceptable > optimisations to it. > > Flame away, I'm sure there are some interesting contrary > points of view! > -- > Jonathan Bromley, Consultant >Hi Jonathan, What about a 4046 type two PLL phase comparator? http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf Actually, this is better inplemented as two FFs*, one clocked by the VCO, one by the Reference frequency, but I still claim it's a 'realistic situation'! :-) Cheers, Symon. * http://www.odyseus.nildram.co.uk/Systems_And_Devices_Files/Basic_PLL.pdf look at fig.2.
Reply by ●January 15, 20072007-01-15
> I thought FPGAs might be suitable, but they all appear to try to offer > more than just something like that. Can anybody point me in some rough > direction?You need SPLD's simple programmable logic devices like the 22v10 or 16v8 (which I am using for my designs). You can get them at jameco,allect or better yet: EBAY
