Browsing the 'cyclone device handbook' I spent a great length to find : -the max current for each supply ( VCCIO & VCCINT ) -the expected clocking frequency at the input. I'm aware that 1MHz may not be sufficient to PLL it up to 400MHz or such. to little avail. While I can live with 2 switchmode supplies generating 1.5V and 3.3V at 2A each, and a generic 8pin socket to swap oscillators for a prototype, the documentation is somehow inclomplete. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Altera Cyclone data is incomplete or messy
Started by ●January 11, 2004
Reply by ●January 12, 20042004-01-12
Rene Tschaggelar wrote:> > Browsing the 'cyclone device handbook' I spent a great > length to find : > -the max current for each supply ( VCCIO & VCCINT ) > -the expected clocking frequency at the input. I'm aware > that 1MHz may not be sufficient to PLL it up to 400MHz > or such. > > to little avail. While I can live with 2 switchmode supplies > generating 1.5V and 3.3V at 2A each, and a generic 8pin > socket to swap oscillators for a prototype, the documentation > is somehow inclomplete.I don't think anyone publishes a *max* current for FPGAs. This depends greatly on the design and the clock speed. It even depends on the loading on the IO lines. But one way you can set a ceiling is to figure out the maximum dissipation the package can provide and assume that can come from either of the two supplies. The may be very conservative, but it will give you a *maximum*.
Reply by ●January 12, 20042004-01-12
Rene Tschaggelar <none@none.none> wrote in message news:41c489438e778508c6ca433ed9cabaf5@news.teranews.com...> Browsing the 'cyclone device handbook' I spent a great > length to find : > -the max current for each supply ( VCCIO & VCCINT )Rene, there's a power consumption spreadsheet downloadable for the Cyclone which will give you figures for your application.> -the expected clocking frequency at the input. I'm aware > that 1MHz may not be sufficient to PLL it up to 400MHz > or such.The PLL output is Input MHz * M/(N * post_scale_counter) where M = 2 to 32, N and post_scale_counter = 1 to 32 I'm pretty sure I got this from the data sheets. Have you checked you've got the latest version, they seem to update them fairly regularly. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' dev board www.nialstewartdevelopments.co.uk
Reply by ●January 12, 20042004-01-12
Ralph Malph wrote:> Rene Tschaggelar wrote: > >>Browsing the 'cyclone device handbook' I spent a great >>length to find : >>-the max current for each supply ( VCCIO & VCCINT ) >>-the expected clocking frequency at the input. I'm aware >> that 1MHz may not be sufficient to PLL it up to 400MHz >> or such. >> >>to little avail. While I can live with 2 switchmode supplies >>generating 1.5V and 3.3V at 2A each, and a generic 8pin >>socket to swap oscillators for a prototype, the documentation >>is somehow inclomplete. > > > I don't think anyone publishes a *max* current for FPGAs. This depends > greatly on the design and the clock speed. It even depends on the > loading on the IO lines. But one way you can set a ceiling is to figure > out the maximum dissipation the package can provide and assume that can > come from either of the two supplies. The may be very conservative, but > it will give you a *maximum*.At least the earlier Altera FPGAs had graphs. Usually 1/8 th of the cells used, current vs clock. Just multiply by 8 and you're about there. I somewhat doubt everyone makes the prototypes with leads to be connected to a laboratory power supply. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Reply by ●January 13, 20042004-01-13
>> I don't think anyone publishes a *max* current for FPGAs. This depends >> greatly on the design and the clock speed. It even depends on the >> loading on the IO lines. But one way you can set a ceiling is to figure >> out the maximum dissipation the package can provide and assume that can >> come from either of the two supplies. The may be very conservative, but >> it will give you a *maximum*.Does that really get you a max? Suppose heat is the limiting factor on the FPGA, but I run it in a pulse mode. It's active 10% of the time, but working real hard when it's active. The length of the active burst can be long enough to cause trouble for the power supply if it's only beefy enough for the average. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●January 14, 20042004-01-14
Rene Tschaggelar <none@none.none> wrote in message news:<41c489438e778508c6ca433ed9cabaf5@news.teranews.com>...> Browsing the 'cyclone device handbook' I spent a great > length to find : > -the max current for each supply ( VCCIO & VCCINT ) > -the expected clocking frequency at the input. I'm aware > that 1MHz may not be sufficient to PLL it up to 400MHz > or such. > > to little avail. While I can live with 2 switchmode supplies > generating 1.5V and 3.3V at 2A each, and a generic 8pin > socket to swap oscillators for a prototype, the documentation > is somehow inclomplete. > > ReneHi Rene, See section 4 of the Cyclone device handbook. (Available at http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf). Page 4-8 gives the current & power during configuration, and refers you to the Cyclone power calculator spreadsheet for doing what-if analysis on application circuits power and current needs while they're running. That spreadsheet is at: http://www.altera.com/products/devices/cyclone/utilities/power_calculator/cyc-power_calculator.html You'll have to enter what you think are reasonable worst-case numbers in terms of operating frequency, toggle rate, IO standards used etc. to get the current supply info you need. Page 4-31 of the device handbook gives the PLL frequency specs. The input frequency has to be between 15.625 MHz and 464 MHz for the fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the slowest (-8) speed grade. See http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details. Regards, Vaughn Altera
Reply by ●January 14, 20042004-01-14
Vaughn Betz wrote:> Rene Tschaggelar <none@none.none> wrote in message news:<41c489438e778508c6ca433ed9cabaf5@news.teranews.com>... > >>Browsing the 'cyclone device handbook' I spent a great >>length to find : >>-the max current for each supply ( VCCIO & VCCINT ) >>-the expected clocking frequency at the input. I'm aware >> that 1MHz may not be sufficient to PLL it up to 400MHz >> or such. >> >>to little avail. While I can live with 2 switchmode supplies >>generating 1.5V and 3.3V at 2A each, and a generic 8pin >>socket to swap oscillators for a prototype, the documentation >>is somehow inclomplete. > > Hi Rene, > > See section 4 of the Cyclone device handbook. (Available at > http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf). Page 4-8 > gives the current & power during configuration, and refers you to the > Cyclone power calculator spreadsheet for doing what-if analysis on > application circuits power and current needs while they're running.Thanks. I saw the maximum configuration currents but found them not really usefull for a non-powersaving application. I admittedly only scanned the document for 'mA'.> > That spreadsheet is at: > http://www.altera.com/products/devices/cyclone/utilities/power_calculator/cyc-power_calculator.html > > You'll have to enter what you think are reasonable worst-case numbers > in terms of operating frequency, toggle rate, IO standards used etc. > to get the current supply info you need.Thanks. Neither really binding numbers as liability is denied, nor useable without Excel. I'll be warned. I'll start with a pcb prototype where some space is reserved for heatsink mounting holes plus some screw power terminals in case the 2A switcher comes to its limit.> > Page 4-31 of the device handbook gives the PLL frequency specs. The > input frequency has to be between 15.625 MHz and 464 MHz for the > fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the > slowest (-8) speed grade. See > http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details.Thanks. These numbers somehow slipped me, even though I scanned the document for 'PLL'. Too many occurences of it, I guess. Rene
Reply by ●January 14, 20042004-01-14
Hal Murray wrote:> > >> I don't think anyone publishes a *max* current for FPGAs. This depends > >> greatly on the design and the clock speed. It even depends on the > >> loading on the IO lines. But one way you can set a ceiling is to figure > >> out the maximum dissipation the package can provide and assume that can > >> come from either of the two supplies. The may be very conservative, but > >> it will give you a *maximum*. > > Does that really get you a max? > > Suppose heat is the limiting factor on the FPGA, but I run it in > a pulse mode. It's active 10% of the time, but working real hard > when it's active. The length of the active burst can be long > enough to cause trouble for the power supply if it's only beefy > enough for the average.So then you know that this is the case and you will adjust the calculations accordingly, right?
Reply by ●January 14, 20042004-01-14
That posting suggested to deduce the max operating power backwards from the package thermal resistance. Do NOT do that ! Package choice is dominated by cost and price consideration, both on the part of the chip manufacturer and on the part of the user. To make the assumption "because it comes in this high thermal resistance package, it will never dissipate more than x Watts" is, excuse the word, silly. Most FPGAs these days can be melted down by a crazy (but legitimate) design running at an outrageous ( but legitimate) clock frequency. It's up to the user to keep the junction temperature within spec. All we manufacturers can do is give you the best analysis tools we can come up with... Peter Alfke, Xilinx ============================= Ralph Malph wrote:> But one way you can set a ceiling is to figure > out the maximum dissipation the package can provide and assume that can come from either of the two supplies. The may be very conservative, but > it will give you a *maximum*.
Reply by ●January 14, 20042004-01-14
Peter Alfke wrote:> That posting suggested to deduce the max operating power backwards from > the package thermal resistance. > Do NOT do that ! > Package choice is dominated by cost and price consideration, both on the > part of the chip manufacturer and on the part of the user. > To make the assumption "because it comes in this high thermal resistance > package, it will never dissipate more than x Watts" is, excuse the > word, silly. > Most FPGAs these days can be melted down by a crazy (but legitimate) > design running at an outrageous ( but legitimate) clock frequency. > It's up to the user to keep the junction temperature within spec. All we > manufacturers can do is give you the best analysis tools we can come up with...Thanks Peter, the first sensible answer. What is wrong with a simple formula ? Eg Imax = Io + 4mA/Mhz + I/O_load. It'd help specifying the power supply as well as the heatsink. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
