Ethernet Interface

Is it possible to interface the Ethernet directly to the FPGA instead
of the doing it through the Power PC processor or any other Processor?
If yes, kindly throw some light on the same.

thanks in advance.

Surya <aswingopalan@gmail.com> wrote:

> Is it possible to interface the Ethernet directly to the FPGA instead
> of the doing it through the Power PC processor or any other Processor?
> If yes, kindly throw some light on the same.

Did you do some basic googling befor asking?
Start e.g. at http://www.fpga4fun.com/
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Hi Surya,

Are you aware that the Xilinx Virtex-4 and Virtex-5 FPGA have an embedded 
EMAC block?  Here is a great article to serve as a starting point: 
http://www.xilinx.com/publications/xcellonline/xcell_59/xc_pdf/p054-056_59-McKay.pdf

-David

"Surya" <aswingopalan@gmail.com> wrote in message 
news:1169033036.685087.68370@51g2000cwl.googlegroups.com...
>
> Is it possible to interface the Ethernet directly to the FPGA instead
> of the doing it through the Power PC processor or any other Processor?
> If yes, kindly throw some light on the same.
>
> thanks in advance.
> 

Using an embedded processor is the natural way to use these interfaces,
why do you want to omit it?  Also, the embedded hard EMACs are really
meant for GBit ethernet, sure you can use them for 10/100 but why?


Surya wrote:
> Is it possible to interface the Ethernet directly to the FPGA instead
> of the doing it through the Power PC processor or any other Processor?
> If yes, kindly throw some light on the same.
> 
> thanks in advance.

Dear David,

    Thank you for your link. It was good. I was aware of the EMACs
present in the Virtex 4 and 5. But i was wondering whether it would be
efficient to write the protocol handler to (removing and addition of
header and footer in simple terms) in the FPGA directly or in the PPC.
If it is in PPC i would not be able to use Virtex 5 and hence the EMAC.


   Kindly advise.


Aswin

davide wrote:
> Hi Surya,
>
> Are you aware that the Xilinx Virtex-4 and Virtex-5 FPGA have an embedded
> EMAC block?  Here is a great article to serve as a starting point:
> http://www.xilinx.com/publications/xcellonline/xcell_59/xc_pdf/p054-056_59-McKay.pdf
>
> -David
>
> "Surya" <aswingopalan@gmail.com> wrote in message
> news:1169033036.685087.68370@51g2000cwl.googlegroups.com...
> >
> > Is it possible to interface the Ethernet directly to the FPGA instead
> > of the doing it through the Power PC processor or any other Processor?
> > If yes, kindly throw some light on the same.
> >
> > thanks in advance.
> >

Aswin,

Lets take the Virtex-5 LX50T as an example.  You could utilize a soft 
processor core(MicroBlaze) within the fabric for your packet processing and 
interface that to the embedded EMAC.  Take a look at XAPP-443 
(http://www.xilinx.com/bvdocs/appnotes/xapp443.pdf).  This provides a good 
example of how a soft processor can be designed to manage the EMAC 
configuration registers, generate frames, edit frames, etc and provides a 
seemless interface to the EMAC.

In terms of efficiency (speed), it is a matter of knowing what your 
throughput needs are for the uP and simulating.  In terms of efficiency for 
additional hardware requirements and board area, I think the FPGA is more 
practical.

-David

"Surya" <aswingopalan@gmail.com> wrote in message 
news:1169186710.800606.31640@v45g2000cwv.googlegroups.com...
> Dear David,
>
>    Thank you for your link. It was good. I was aware of the EMACs
> present in the Virtex 4 and 5. But i was wondering whether it would be
> efficient to write the protocol handler to (removing and addition of
> header and footer in simple terms) in the FPGA directly or in the PPC.
> If it is in PPC i would not be able to use Virtex 5 and hence the EMAC.
>
>
>   Kindly advise.
>
>
> Aswin
>
> davide wrote:
>> Hi Surya,
>>
>> Are you aware that the Xilinx Virtex-4 and Virtex-5 FPGA have an embedded
>> EMAC block?  Here is a great article to serve as a starting point:
>> http://www.xilinx.com/publications/xcellonline/xcell_59/xc_pdf/p054-056_59-McKay.pdf
>>
>> -David
>>
>> "Surya" <aswingopalan@gmail.com> wrote in message
>> news:1169033036.685087.68370@51g2000cwl.googlegroups.com...
>> >
>> > Is it possible to interface the Ethernet directly to the FPGA instead
>> > of the doing it through the Power PC processor or any other Processor?
>> > If yes, kindly throw some light on the same.
>> >
>> > thanks in advance.
>> >
>