Generation of Divided-by-3 clock

Hi,

I need to generate a 70MHz clock from 210MHz. Is there any way to
generate it rather than using a DCM.

Thanks, 

Sudheer

It's very simple:
Take two Logic Cells (each a LUT and a Flip-flop) and feed both Q
outputs to the inputs of both LUTs.
Imagine any one (of many possible)  sequence on the two Q outputs that
repeats after 3 states.
Then implement the required logic in each LUT.
I don't want to make it too trivially simple for you. A little thinking
strengthens the brain.
Peter Alfke

On Jan 17, 9:20 pm, "K. Sudheer Kumar" <ksudheerku...@gmail.com>
wrote:
> Hi,
>
> I need to generate a 70MHz clock from 210MHz. Is there any way to
> generate it rather than using a DCM.
> 
> Thanks,
> 
> Sudheer

This is not a hard problem if you don't care about duty cycle.  I'll
leave that for you to logic out, but if you need 50% duty cycle then
there are tricks.

Peter Alfke from Xilinx wrote an excellent article about clock dividers
titled "Unusual Clock Dividers."  It was published the Xilinx's Xcell
Journal.  I believe issue 33, but it appears Xilinx has gotten rid of
that article as it's archives don't go back far at all anymore.

You could probably find it through some googling, but this brings up
another point: Why would Xilinx remove it's archives?  It's not like
the material was dated.

That particular article has been of use to me several times.  Peter
wrote a great article.  I'd like to see it come back.

-Arlen


K. Sudheer Kumar wrote:
> Hi,
>
> I need to generate a 70MHz clock from 210MHz. Is there any way to
> generate it rather than using a DCM.
> 
> Thanks, 
> 
> Sudheer

Hi Peter,

Thanks for your suggestion. I would appreciate your providing me a copy
of your article "Unusual Clock Dividers".

Sudheer.

Peter Alfke wrote:
> It's very simple:
> Take two Logic Cells (each a LUT and a Flip-flop) and feed both Q
> outputs to the inputs of both LUTs.
> Imagine any one (of many possible)  sequence on the two Q outputs that
> repeats after 3 states.
> Then implement the required logic in each LUT.
> I don't want to make it too trivially simple for you. A little thinking
> strengthens the brain.
> Peter Alfke
>
> On Jan 17, 9:20 pm, "K. Sudheer Kumar" <ksudheerku...@gmail.com>
> wrote:
> > Hi,
> >
> > I need to generate a 70MHz clock from 210MHz. Is there any way to
> > generate it rather than using a DCM.
> > 
> > Thanks,
> > 
> > Sudheer

sudheer schrieb:

> Hi Peter,
>
> Thanks for your suggestion. I would appreciate your providing me a copy
> of your article "Unusual Clock Dividers".
>
> Sudheer.
dear Sudheer,

isnt goodle your friend too?

http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcell/xl33/xl33_30.pdf

Antti

"gallen" <arlencox@gmail.com> wrote in message 
news:1169101376.940807.115180@v45g2000cwv.googlegroups.com...
>
> You could probably find it through some googling, but this brings up
> another point: Why would Xilinx remove it's archives?  It's not like
> the material was dated.
>
Stop whining and start searching! :-)

http://web.archive.org/web/20050404010919/www.xilinx.com/xcell/xl33/xl33_30.pdf

HTH, Syms. 

Hi,
I studied this article. It is very interesting, and the resources
consumption is very low.
For a general purpose, I think Anydivider can help.
In this case, just enter "3", and then get the verilog code and the
waveform.
For more features, please visit
http://www.topweaver.com/doc/tad/tad.htm
Download http://www.topweaver.com/download.htm

TAD

"Antti =D0=B4=B5=C0=A3=BA
"
> sudheer schrieb:
>
> > Hi Peter,
> >
> > Thanks for your suggestion. I would appreciate your providing me a copy
> > of your article "Unusual Clock Dividers".
> >
> > Sudheer.
> dear Sudheer,
>
> isnt goodle your friend too?
>
> http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcell/xl=
33/xl33_30.pdf
>=20
> Antti

module clock_div3
      (
      clock_in,
      clock_out
      );

input            clock_in;
output           clock_out;

reg              clock_out;
reg      [2:1]   d_pos;
reg      [2:1]   d_neg;


always @ (posedge clock_in)
  case (d_pos)
  2'b00:    d_pos[2:1]  <= 2'b01;
  2'b01:    d_pos[2:1]  <= 2'b11;
  default:  d_pos[2:1]  <= 2'b00;
  endcase

always @ (negedge clock_in)
  case (d_neg)
  2'b00:    if (d_pos[1]) d_neg[2:1]  <= 2'b01;
  2'b01:    d_neg[2:1]  <= 2'b10;
  default:  d_neg[2:1]  <= 2'b00;
  endcase

always @ (posedge clock_in or posedge (d_neg[1] & !clock_in))
  if (d_neg[1] & !clock_in)
    clock_out  <= 1'b0;
  else
    if (!d_pos[1]) clock_out  <= 1'b1;

endmodule

I see all these references to my old article in XCell magazine, and I
enjoy the positive comments.
But: In almost all cases, there is no need for 50% duty cycle. The
natural 33/66% duty cycle of a simple divide-by-three circuit is
acceptable, especially at such low frequencies as 70 MHz.

Here is one of the simplest implementations:
Two flip-flops QA and QB,  QA feeds the D-input of QB (shift register)
The NOR of QA and QB feeds the D input of QA.
This circuit also recovers from the illegal state of both QA and QB
being High.
Peter Alfke


On Jan 18, 9:26 am, "visiblepulse" <t...@visiblepulse.com> wrote:
> module clock_div3
>       (
>       clock_in,
>       clock_out
>       );
>
> input            clock_in;
> output           clock_out;
>
> reg              clock_out;
> reg      [2:1]   d_pos;
> reg      [2:1]   d_neg;
>
> always @ (posedge clock_in)
>   case (d_pos)
>   2'b00:    d_pos[2:1]  <= 2'b01;
>   2'b01:    d_pos[2:1]  <= 2'b11;
>   default:  d_pos[2:1]  <= 2'b00;
>   endcase
>
> always @ (negedge clock_in)
>   case (d_neg)
>   2'b00:    if (d_pos[1]) d_neg[2:1]  <= 2'b01;
>   2'b01:    d_neg[2:1]  <= 2'b10;
>   default:  d_neg[2:1]  <= 2'b00;
>   endcase
>
> always @ (posedge clock_in or posedge (d_neg[1] & !clock_in))
>   if (d_neg[1] & !clock_in)
>     clock_out  <= 1'b0;
>   else
>     if (!d_pos[1]) clock_out  <= 1'b1;
> 
> endmodule

Thanks to alll for sending their comments/Useful Links.

I'm getting worried about the phase misalignment of divided clock w.r.t
the source clock because of combinational logic associated with the
output.

I would like to welcome your suggestions/comments on this

Note: Duty cycle with 33%, 66% will not be worked out in our case, so
badly I'm in need of clock with 50%dutycycle.

Thanks a lot once again,
Sudheer.