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Phasse Detector

Started by axalay ●January 19, 2007
Share please the circuit of the phase detector (I do not want to invent
a bicycle). Any of the circuits laid out in an Internet does not work.
Reply by motty ●January 19, 20072007-01-19
axalay wrote:

> Share please the circuit of the phase detector (I do not want to invent
> a bicycle). Any of the circuits laid out in an Internet does not work.


XOR?

Short non-descriptive posts get you short non-descriptive answers.   : )
Reply by Tim ●January 19, 20072007-01-19
> axalay wrote:
>> Share please the circuit of the phase detector (I do not want to invent
>> a bicycle). Any of the circuits laid out in an Internet does not work.
> 


Try the data sheet for the Analog Devices phase comparator. Google for it!
Reply by -jg ●January 19, 20072007-01-19
axalay wrote:

> Share please the circuit of the phase detector (I do not want to invent
> a bicycle). Any of the circuits laid out in an Internet does not work.


Google HC4046
Reply by PeteS ●January 19, 20072007-01-19
axalay wrote:

> Share please the circuit of the phase detector (I do not want to invent
> a bicycle). Any of the circuits laid out in an Internet does not work.
> 


Homework?

Cheers

PeteS
Reply by Peter Alfke ●January 19, 20072007-01-19
The classical 30+-year old phase/frequency comparator is the Motorola
MC4044.
(I copied its structure into my Xilinx app note XAPP028)
Just google both these circuits...
Peter Alfke


On Jan 19, 1:58 pm, PeteS <peter.smith8...@ntlworld.com> wrote:

> axalay wrote:
> > Share please the circuit of the phase detector (I do not want to invent
> > a bicycle). Any of the circuits laid out in an Internet does not work.Homework?
> 
> Cheers
> 
> PeteS
Reply by PeteS ●January 19, 20072007-01-19
Peter Alfke wrote:

> The classical 30+-year old phase/frequency comparator is the Motorola
> MC4044.
> (I copied its structure into my Xilinx app note XAPP028)
> Just google both these circuits...
> Peter Alfke
> 
> 
> On Jan 19, 1:58 pm, PeteS <peter.smith8...@ntlworld.com> wrote:
>> axalay wrote:
>>> Share please the circuit of the phase detector (I do not want to invent
>>> a bicycle). Any of the circuits laid out in an Internet does not work.Homework?
>> Cheers
>>
>> PeteS
> 


Heh heh

The MC4044 is my favourite phase detector whether in a MC4044 package or 
modelled in an FPGA.

Cheers

PeteS
Reply by axalay ●January 20, 20072007-01-20
XOR - is not detrct + or - phase shift. And I not use external phase
detect chips. I whant do it in FPGA. And structure of phase detector
from XAPP028 is not work! 

Vasiliy
Reply by JustJohn ●January 20, 20072007-01-20
axalay wrote:

> XOR - is not detrct + or - phase shift. And I not use external phase
> detect chips. I whant do it in FPGA. And structure of phase detector
> from XAPP028 is not work!
>
> Vasiliy


Vasiliy,
  It works just fine, although the timing tools will give you grief
over the combinatorial feedback loop, and simulators may choke on it.
You might double check that your PU/PD are pumping in the right
direction, and that your external analog filter is correct.

An altermative implementation uses a pair of FFs, one clocked high by
your feedback clock, one clocked high by the reference clock, and both
asynchronously reset when both are high. PU and PD are decoded when one
or the other FF is high. Slightly more simulator friendly.

Just John
Reply by -jg ●January 20, 20072007-01-20
JustJohn wrote:

> axalay wrote:
> > XOR - is not detrct + or - phase shift. And I not use external phase
> > detect chips. I whant do it in FPGA. And structure of phase detector
> > from XAPP028 is not work!
> >
> > Vasiliy
>
> Vasiliy,
>   It works just fine, although the timing tools will give you grief
> over the combinatorial feedback loop, and simulators may choke on it.
> You might double check that your PU/PD are pumping in the right
> direction, and that your external analog filter is correct.
>
> An altermative implementation uses a pair of FFs, one clocked high by
> your feedback clock, one clocked high by the reference clock, and both
> asynchronously reset when both are high. PU and PD are decoded when one
> or the other FF is high. Slightly more simulator friendly.


The HC4046 uses this topology.
The OP could also drop in a 4046, and get the system working, then
transfer
pieces into the FPGA. That's a good way to confirm other parts are OK,
plus you have a working reference for things like phase noise in the
phase detector/charge pump sections.
FPGA pumps will use the FPGA rails, so for lower noise (if that
matters)
you can drive analog switches from the FPGA

-jg