Simulation of DCM with Xilinx 8.2 and Modelsim 6.1

Hello,

for some reason I still don't understand, when I simulate my Post Place
& Route model, the DCM that was configured to introduce a delay of 2ns
does not work properly. It shows a delay of 1.3 ns instead.

This is the code that I use to instantiate the DCM:

-- DCM with fixed positive phase shift (2 ns, configured with Coregen)
Inst_my_dcm_a: my_dcm PORT MAP(
	CLKIN_IN => dsp_clk_pad_a,
	RST_IN => rst,
	CLKIN_IBUFG_OUT => open,
	CLK0_OUT => dsp_clk_a,
	LOCKED_OUT => LOCKED_a
);

The input clock has a period of 10 ns (100 Mhz).

In Modelsim, this is the route and the delays from the clock input pad
until some point in the circuit:

0.000 ns 	@ /tim_top_tb/dspa_clk    (<- this is the input clock signal
in the testbench)
0.000 ns 	@ /tim_top_tb/i_tim_top/dsp_clk_pad_a  (<- this is the input
pad at the top module instance)
0.000 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clkin_ibufg_inst/i
0.181 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clkin_ibufg_inst/o
0.181 ns	@ /tim_top_tb/i_tim_top/dsp_clk_pad_a_inbuf
0.181 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst_clkin_buf/i
1.618 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst_clkin_buf/o
1.618 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst_clkin_buf_11712
1.618 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/clkin
1.618 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/clkin_ipd
1.618 ns	@
/tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/i_clock_divide_by_2/clock
1.618 ns	@
/tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/i_clock_divide_by_2/clock_out
1.618 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/clkin_div
3.649 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/clkin_ps
3.649 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/clk0_out
8.601 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_dcm_inst/clk0
8.601 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clk0_buf
8.601 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clk0_bufg_inst_i0_used/i
9.440 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clk0_bufg_inst_i0_used/o
9.440 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clk0_bufg_inst_i0_inv
9.440 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clk0_bufg_inst/i0
10.029 ns	@ /tim_top_tb/i_tim_top/inst_my_dcm_a_clk0_bufg_inst/o
10.029 ns	@ /tim_top_tb/i_tim_top/dsp_clk_a       (<- this is the name
of the signal that I actually use in my design, the one that I want to
delay 2 ns)
10.029 ns	@ /tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16_clkinv/i
11.401 ns	@ /tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16_clkinv/o
11.401 ns	@
/tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16_clkinv_38490
11.401 ns	@ /tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16/clk
11.401 ns	@
/tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16/clk_resolved
11.401 ns	@ /tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16/clk_ipd
11.401 ns	@ /tim_top_tb/i_tim_top/g_dsp_n_0_i_dsp_n_busin_16/clk_dly
(<- this is the clock input to a register)

Can anyone tell me what I am missing? Why the delay between
/tim_top_tb/dspa_clk and /tim_top_tb/i_tim_top/dsp_clk_a is 0.029 ns
instead of 2 ns?

Regards.