xilinx 8.2 xps debug problems

Hi

I am working with an xilinx xup board. 8.2 sp1 ise + 8.2 edk.
I am starting creating a design with ppc running from ddr ram, sysace and
uart for output. Starting the debugger with:
xmd -xmp system.xmp -opt etc/xmd_ppc405_0.opt
with example application works.

Closing the project adding a new plb peripherial template with 4x32
registers no interrupts. Reopening the project. Download bitstream.
Starting the debugger again gives:

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       05059093          16        XCF32P
 2       0a001093           8        System_ACE
 3       0127e093          14        XC2VP30


Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000

make -f system.make clean doesn't help.

Any idea why the jtag autodetection fails after adding an core to the plb
bus?

Thanks
Ludwig

On Thu, 25 Jan 2007 18:39:32 +0100, Ludwig Lenz
<llenz@vlsi.informatik.tu-darmstadt.de> wrote:

>Hi
>
>I am working with an xilinx xup board. 8.2 sp1 ise + 8.2 edk.
>I am starting creating a design with ppc running from ddr ram, sysace and
>uart for output. Starting the debugger with:
>xmd -xmp system.xmp -opt etc/xmd_ppc405_0.opt
>with example application works.
>
>Closing the project adding a new plb peripherial template with 4x32
>registers no interrupts. Reopening the project. Download bitstream.

When downloading bitstream , are you using Impact and the JTAG chain?
If so, you need the "Pulse PROG" option set to start the PPC properly
(using other tools there may be an equivalent setting). 
Symptoms if you don't are just what you describe.

Never did get a satisfactory explanation as to what this did or why, but
it fixed the problem here.

- Brian

Ludwig Lenz wrote:
> Hi
> 
> I am working with an xilinx xup board. 8.2 sp1 ise + 8.2 edk.
> I am starting creating a design with ppc running from ddr ram, sysace and
> uart for output. Starting the debugger with:
> xmd -xmp system.xmp -opt etc/xmd_ppc405_0.opt
> with example application works.
> 
> Closing the project adding a new plb peripherial template with 4x32
> registers no interrupts. Reopening the project. Download bitstream.
> Starting the debugger again gives:
> 
> JTAG chain configuration
> --------------------------------------------------
> Device   ID Code        IR Length    Part Name
>  1       05059093          16        XCF32P
>  2       0a001093           8        System_ACE
>  3       0127e093          14        XC2VP30
> 
> 
> Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
> 
> make -f system.make clean doesn't help.
> 
> Any idea why the jtag autodetection fails after adding an core to the plb
> bus?
> 
> Thanks
> Ludwig

I only get this error if there is no bitstream downloaded to the FPGA.
Look if the red LED (D4 - DONE) near config DIP-switches is on.

HTH
    Thomas