Typical clock frequencies of FPGA designs

"Gabor" <gabor@alacron.com> wrote:

>I'm guessing the CPLD in this case was
>chosen for minimal power consumption.  At 1024 Hz. there are
>a number of microcontrollers that would do the job of a clock
>quite nicely.

I have a CPLD design with an input clock 153.6kHz (16 x 9600) and most of
the design is running at 75Hz. 

The CPLD was chosen to be big enough to fit the design and a CPLD was
chosen over a microcontroller because microcontrollers need 'software' and
in some organisations the amount of crap you have to go through to use any
kind of 'software' in a design makes a programmable logic solution
attractive. 
-- 

Andreas Ehliar wrote:

> Hi, I've been wondering for a while if there is any data about
> typical clock frequencies of FPGA designs for various FPGA
> devices.
> 
> What I'm curious about is if there is any sort of published
> statistics about the clock frequencies used in different FPGA
> designs on different FPGA architectures.
> 
> Basically I'd like to have some empirical data as to what to
> consider absurdly low, low, normal or high or extremely high in
> terms of clock frequency in a certain FPGA device.
> 
> This is of course more complicated if you consider multiple
> clock domains, design complexity, hard IP cores running
> at speeds much higher than the surrounding logic, etc.
> 
> From the limited experience I have I would consider designs
> running at over say 200 MHz in a Virtex-4 to be high speed
> designs and designs running at lower than 100 MHz in such a
> device to be low speed but I may be off the mark here by a
> significant margin :)
> 
> That is why I'd really like to hear if anyone knows of any
> published statistics about this subject.
> 
> /Andreas


For V4, 200 MHz isn't high speed, in fact it is only half the clock rate 
the DSP48's BRAMs and DCMs are spec'd at for the slowest speed grade. 
At 200 Mhz, you don't really even need to worry much about placement as 
long as you are reasonably careful with the design.  I'd put the 
dividing line for high speed somewhat over 300 MHz, in other words where 
you start to have to worry about placement in order to meet timing.  My 
floating point FFT kernel makes timing in a -10 part at 400MHz: it is 
limited by the clock speed of the BRAM and DSP48s, that probably counts 
for extremely high, as the clock speed is limited by the minimum clock 
period of the FPGA blocks rather than by the design.  If you stick to 
just LUTs, you can push it quite a bit higher, but then you give up the 
big features too.  The V4 clocks don't really like to be run slower than 
about 150 MHz.  I'd consider anything less than that to be quite low.

The flip side to this is power consumption.  At high utilization and 
high clock rates, cooling can become a challenge.

FPGAs are much different than CPLDs as far as clocking goes too.  FPGAs 
have an abundance of flip-flops, as well as clock managers that can 
multiply the input clock.  This makes it very attractive to use a 
multiplied clock in order to reduce the footprint of the logic, which 
can often get you into a significantly smaller device.