Hello, I have been using batch files to handle the build process with a Xilinx flow for a while. Now I want to move to a more sophisticated approach to handle dependencies better. I don't really want to use makefiles, I find find them too arcane and hard to write. That's where SCons comes in. It seems like a great alternative to make (plus it's written in Python and I've been wanting to learn that language for a while now). Does anyone have any experience with SCons and ideally, scripts they would like to share? Example scripts for a fpga flow would certainly help with the learning curve. Thanks. Patrick Dubois
SCons build tool as an alternative to makefiles
Started by ●February 28, 2007
Reply by ●March 1, 20072007-03-01
"Patrick Dubois" <prdubois@gmail.com> writes:> Hello, > > I have been using batch files to handle the build process with a > Xilinx flow for a while. Now I want to move to a more sophisticated > approach to handle dependencies better. >This has just reminded me of something I discovered recently: Neither PAR nor TRCE return an error if the design fails timing, so any script/makefile which relies on the return code being non-zero as an error (like... well... just about anything sane!) will carry on through it's script as if everything is OK! You have to parse the PAR logfile for "No timing errors found" if you want to be sure. I have a change request in to fix this, please add your weight to the request (unless you think I'm bonkers for thinking that failing timing is an error!) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Reply by ●March 1, 20072007-03-01
> This has just reminded me of something I discovered recently: > > Neither PAR nor TRCE return an error if the design fails timing, so > any script/makefile which relies on the return code being non-zero as > an error (like... well... just about anything sane!) will carry on > through it's script as if everything is OK! > > You have to parse the PAR logfile for "No timing errors found" if you > want to be sure. > > I have a change request in to fix this, please add your weight to the > request (unless you think I'm bonkers for thinking that failing timing > is an error!) > > Cheers, > MartinVery good point. I always try to remind new engineers here to always remember to check the timing report part of the PAR log to make sure that there are no timing errors. I'll try to open a webcase on the issue. Do you have a CR number I can refer to? Patrick
Reply by ●March 2, 20072007-03-02
"Patrick Dubois" <prdubois@gmail.com> writes:>> This has just reminded me of something I discovered recently: >> >> Neither PAR nor TRCE return an error if the design fails timing, so >> any script/makefile which relies on the return code being non-zero as >> an error (like... well... just about anything sane!) will carry on >> through it's script as if everything is OK! >> >> You have to parse the PAR logfile for "No timing errors found" if you >> want to be sure. >> >> I have a change request in to fix this, please add your weight to the >> request (unless you think I'm bonkers for thinking that failing timing >> is an error!) >> >> Cheers, >> Martin > > Very good point. I always try to remind new engineers here to always > remember to check the timing report part of the PAR log to make sure > that there are no timing errors. I'll try to open a webcase on the > issue. Do you have a CR number I can refer to? >Not yet, I'll try and remember to post it here when I get it... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Reply by ●March 2, 20072007-03-02
A long time ago we were bitten by this, and we added this to our Makefile to check that PAR met timing: # # Place and route the mapped netlist into the device # %_routed.ncd: %.ncd par -w $(PAR_FLAGS) $< $@ @grep 'All constraints were met' $*_routed.par > /dev/null || false Granted, it relies on Xilinx not changin the wording of the 'All constraints...' line. cheers, aaron On Mar 2, 8:56 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:> "Patrick Dubois" <prdub...@gmail.com> writes: > >> This has just reminded me of something I discovered recently: > > >> Neither PAR nor TRCE return an error if the design fails timing, so > >> any script/makefile which relies on the return code being non-zero as > >> an error (like... well... just about anything sane!) will carry on > >> through it's script as if everything is OK! > > >> You have to parse the PAR logfile for "No timing errors found" if you > >> want to be sure. > > >> I have a change request in to fix this, please add your weight to the > >> request (unless you think I'm bonkers for thinking that failing timing > >> is an error!) > > >> Cheers, > >> Martin > > > Very good point. I always try to remind new engineers here to always > > remember to check the timing report part of the PAR log to make sure > > that there are no timing errors. I'll try to open a webcase on the > > issue. Do you have a CR number I can refer to? > > Not yet, I'll try and remember to post it here when I get it... > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html
Reply by ●March 2, 20072007-03-02
On Mar 1, 7:03 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:> "Patrick Dubois" <prdub...@gmail.com> writes: > > Hello, > > > I have been using batch files to handle the build process with a > > Xilinx flow for a while. Now I want to move to a more sophisticated > > approach to handle dependencies better. > > This has just reminded me of something I discovered recently: > > Neither PAR nor TRCE return an error if the design fails timing, so > any script/makefile which relies on the return code being non-zero as > an error (like... well... just about anything sane!) will carry on > through it's script as if everything is OK! > > You have to parse the PAR logfile for "No timing errors found" if you > want to be sure. > > I have a change request in to fix this, please add your weight to the > request (unless you think I'm bonkers for thinking that failing timing > is an error!)Failing timing is an error, but personally I don't want the tool to return an error code just because of timing errors: * I have seen people over-constraining designs. If par doesn't meet the over-constrained timing but meets the desired timing, I don't want my script to stop. * If I am in the lab debugging my design and want to quickly try out a few things, I don't want my script to stop just because one net failed timing by several ps. Cheers, Jim http://home.comcast.net/~jimwu88/tools/
Reply by ●March 5, 20072007-03-05
Martin Thompson <martin.j.thompson@trw.com> writes: I remembered :-) CR # 435345 Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Reply by ●March 5, 20072007-03-05
"Jim Wu" <jimwu88NOOOSPAM@yahoo.com> writes:> On Mar 1, 7:03 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: >> "Patrick Dubois" <prdub...@gmail.com> writes: >> > Hello, >> >> > I have been using batch files to handle the build process with a >> > Xilinx flow for a while. Now I want to move to a more sophisticated >> > approach to handle dependencies better. >> >> This has just reminded me of something I discovered recently: >> >> Neither PAR nor TRCE return an error if the design fails timing, so >> any script/makefile which relies on the return code being non-zero as >> an error (like... well... just about anything sane!) will carry on >> through it's script as if everything is OK! >> >> You have to parse the PAR logfile for "No timing errors found" if you >> want to be sure. >> >> I have a change request in to fix this, please add your weight to the >> request (unless you think I'm bonkers for thinking that failing timing >> is an error!) > > Failing timing is an error, but personally I don't want the tool to > return an error code just because of timing errors:OK< I can see people want to work in different ways, but to have the *default* situation of "no error on error" is counter-intuitive!> * I have seen people over-constraining designs. If par doesn't meet > the over-constrained timing but meets the desired timing, I don't want > my script to stop.I do :-) Why overconstrain? If they want some margin on the design, are they be happy with less margin than you asked for?> * If I am in the lab debugging my design and want to quickly try out a > few things, I don't want my script to stop just because one net failed > timing by several ps. >Maybe, that's why one of my suggestions to Xilinx is that they return the timing score, so you can decide how much failure is acceptable (from "0" upwards). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Reply by ●March 5, 20072007-03-05
Just to come back on the subject of Scons for a minute... Any input on that tool? Or does anyone have another suggestion for a make alternative? Thanks. Patrick
Reply by ●March 6, 20072007-03-06
"Patrick Dubois" <prdubois@gmail.com> writes:> Just to come back on the subject of Scons for a minute... Any input on > that tool?It does look neat, but will require some work to make it do what we want I imagine... It also seems to be solving a more difficult problem that FPGA building, which seems (to me) to be a fairly linear series of events where the only dependency is on the previous process.> Or does anyone have another suggestion for a make > alternative? >Why do you dislike make? Personally, I just use a series of batch files... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
