Where can i get free CAN VHDL core

Hi,

I am going through the net to download CAN VHDL core.
HurriCANe is removed from the ESA site, and the link in opencores site
for VHDL CAN core is going to some odd page.

can you please guide me on where i can download this or if anyone does
have these free versions can you mail me ?

Thank you for your time

raju

look in grlib from gaisler research : www.gaisler.com

On Mar 1, 5:39 am, raju.pe...@gmail.com wrote:
> Hi,
>
> I am going through the net to download CAN VHDL core.
> HurriCANe is removed from the ESA site, and the link in opencores site
> for VHDL CAN core is going to some odd page.
>
> can you please guide me on where i can download this or if anyone does
> have these free versions can you mail me ?
>
> Thank you for your time
>
> raju

On Thu, 28 Feb 2007, raju.penum@gmail.com wrote:

"I am going through the net to download CAN VHDL core.
HurriCANe is removed from the ESA site, [..]

[..] or if anyone does
have these free versions can you mail me ?"

HurriCANe is not free.

"and the link in opencores site
for VHDL CAN core is going to some odd page.

can you please guide me on where i can download this [..]"

I shall attach it in a followup to this post, but you may have difficulty 
getting it to work. Xilinx ISE could not manage to fit it onto a Virtex2 
nor a QPro Virtex Rad Hard xqvr300cb228-4 for me during the few minutes I 
tried, but it might be possible to get ISE to get it working for a 
VirtexE if ISE's warnings are surmountable.

Hi

> and the link in opencores site
> for VHDL CAN core is going to some odd page.

You can download the Opencores VHDL CAN core from here:
http://web.archive.org/web/20050407203157/http://www.logic-xpress.com/CAN_VHD.ZIP

(it is an archive of the site from 2005). I have no idea if it works
however. The developer says it is untested, so it probably needs work.

If at all possible, I advise you to use the Verilog version:
http://www.opencores.org/pdownloads.cgi/list/can

I have tested and implemented this (on Xilinx Spartan IIE), and it
works well. You can have a mixed-source project in recent version of
Xilinx tools, so you could combine the Verilog core with the rest of
your code in VHDL. Simulation is a bit more tricky if you only have
the "limited" editions of Modelsim etc.

Tom

Hi,

 Thank you all for your inputs. i did download the code from the path
that you have given me.

Tom, thank you for informing on mixed mode implementation.  i will
look into it, and try to work it out that way.

thanks

raju