Hey Guys, It's a been a while since we had a bypass capacitor religious war, so I thought I'd stir things up a bit! Seriously, I've been reading about X2Y capacitors, and a search of the newsgroup revealed that these very interesting parts have only been mentioned once or twice in passing. (By Austin, natch!) Check out :- http://www.teraspeed.com/publications.html Where they ask you to register for :- http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf Steve Weir does a great job of showing why X2Y caps give you more bang for your buck. As these parts have exceptionally low inductance, they can substantially reduce the number of capacitors AND vias you need, and they quote that :- "Can replace from three to six+ regular caps depending on via and plane geometries" "Vias at $0.005/hole / $0.01 / capacitor typical, often COST MORE than the capacitors they connect!" Here's another interesting article:- http://www.x2y.com/bypass/mount/backside_cap.pdf They recommend using small 'puddles' of copper to connect all the bypass elements together so you can use fewer capacitors but keep the same bypass network performance. Check out http://www.x2y.com/bypass.htm for more articles. AFAICS, the main drawback is that X2Y caps are available in a range of values. This means nutters will use several different values in their bypass networks to create 'resonances' and the like. :-) Anyway, I hope this is of interest, Syms.
Bypass caps, X2Y and 'puddles'.
Started by ●March 1, 2007
Reply by ●March 1, 20072007-03-01
Symon, Another interesting alternative (playstation uses four per big ASIC, and no other caps at all) is: http://www.nec-tokin.com/english/product/cap/proadlizer/index.html Austin
Reply by ●March 1, 20072007-03-01
Symon - On Thu, 1 Mar 2007 13:17:04 -0000, "Symon" <symon_brewer@hotmail.com> wrote:>Hey Guys, >It's a been a while since we had a bypass capacitor religious war, so I >thought I'd stir things up a bit! >Seriously, I've been reading about X2Y capacitors, and a search of the >newsgroup revealed that these very interesting parts have only been >mentioned once or twice in passing. (By Austin, natch!) > >Check out :- >http://www.teraspeed.com/publications.html >Where they ask you to register for :- >http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf > >Steve Weir does a great job of showing why X2Y caps give you more bang for >your buck. As these parts have exceptionally low inductance, they can >substantially reduce the number of capacitors AND vias you need, and they >quote that :- >"Can replace from three to six+ regular caps depending on via and plane >geometries" >"Vias at $0.005/hole / $0.01 / capacitor typical, often COST MORE than the >capacitors they connect!"I saw Steve Weir's presentation on this very subject at an IEEE Santa Clara Valley EMC meeting a year or two ago. Good stuff. You raise an interesting point about costs. We often add up the costs of those things that are easy to tally--parts costs, for example--then forget to account for other things that may be just as significant or more so, such as vias. Another cost that's often poorly accounted for is component placement. Some years ago I worked with an analog designer who was trying to figure out how much it cost an assembly house to place a small discrete component on a board. He asked our assembly house, which declined to give us a precise--or even semi-precise--answer. (Some assembly houses seem to treat their formula for calculating board assembly costs as a trade secret; I guess they're afraid the customers will use the formula to sanity-check future quotes.) This analog designer, a very bright fellow, was not to be deterred by this, and proceeded to create his own formula based on a number of assemblies we'd built (if you try this, it helps when you have some assemblies with only ICs, and other assemblies with ICs plus about 5,000 analog parts). He concluded that while we were paying a penny for a capacitor or resistor, we paid the assembly house 8 or 9 cents to place the part on the board. Maybe this is the correct number and maybe it isn't, but it bolsters your point that reducing total component cost may not lead to the lowest overall assembly cost. Bob Perlman Cambrian Design Works http://www.cambriandesign.com>Here's another interesting article:- >http://www.x2y.com/bypass/mount/backside_cap.pdf > >They recommend using small 'puddles' of copper to connect all the bypass >elements together so you can use fewer capacitors but keep the same bypass >network performance. > >Check out http://www.x2y.com/bypass.htm for more articles. > >AFAICS, the main drawback is that X2Y caps are available in a range of >values. This means nutters will use several different values in their bypass >networks to create 'resonances' and the like. :-) > >Anyway, I hope this is of interest, Syms. >
Reply by ●March 1, 20072007-03-01
Symon wrote:> Hey Guys, > It's a been a while since we had a bypass capacitor religious war, so I > thought I'd stir things up a bit! > Seriously, I've been reading about X2Y capacitors, and a search of the > newsgroup revealed that these very interesting parts have only been > mentioned once or twice in passing. (By Austin, natch!) > > Check out :- > http://www.teraspeed.com/publications.html > Where they ask you to register for :- > http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf > > Steve Weir does a great job of showing why X2Y caps give you more bang for > your buck. As these parts have exceptionally low inductance, they can > substantially reduce the number of capacitors AND vias you need, and they > quote that :- > "Can replace from three to six+ regular caps depending on via and plane > geometries" > "Vias at $0.005/hole / $0.01 / capacitor typical, often COST MORE than the > capacitors they connect!" > > Here's another interesting article:- > http://www.x2y.com/bypass/mount/backside_cap.pdf > > They recommend using small 'puddles' of copper to connect all the bypass > elements together so you can use fewer capacitors but keep the same bypass > network performance. > > Check out http://www.x2y.com/bypass.htm for more articles. > > AFAICS, the main drawback is that X2Y caps are available in a range of > values. This means nutters will use several different values in their bypass > networks to create 'resonances' and the like. :-) > > Anyway, I hope this is of interest, Syms.Interesting. They are correct, but also use a couple of small 'goal post shifting' techniques. * The vias to 'their' caps, have a larger copper cross section, than to other caps. * they choose to compare 100nf (others) against their 56nf. Claiming you double their cap, is not quite correct. What they should compare, is their 56nf, against 2 x 56nF others I agree with this "Mounted ESL for an X2Y� on a 4/6 layer PCB is completely dominated by the attachment inductance..." -jg
Reply by ●March 1, 20072007-03-01
>> Anyway, I hope this is of interest, Syms.There's an interesting link in one of the papers to FastHenry, a free 3D solver, at http://www.fastfieldsolvers.com/
Reply by ●March 2, 20072007-03-02
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:dptdu29sj45cdlj37vmtqjn0nvn8t1p7ro@4ax.com...>> > Another cost that's often poorly accounted for is component placement. > Some years ago I worked with an analog designer who was trying to > figure out how much it cost an assembly house to place a small > discrete component on a board. He asked our assembly house, which > declined to give us a precise--or even semi-precise--answer. (Some > assembly houses seem to treat their formula for calculating board > assembly costs as a trade secret; I guess they're afraid the customers > will use the formula to sanity-check future quotes.) > > This analog designer, a very bright fellow, was not to be deterred by > this, and proceeded to create his own formula based on a number of > assemblies we'd built (if you try this, it helps when you have some > assemblies with only ICs, and other assemblies with ICs plus about > 5,000 analog parts). He concluded that while we were paying a penny > for a capacitor or resistor, we paid the assembly house 8 or 9 cents > to place the part on the board. Maybe this is the correct number and > maybe it isn't, but it bolsters your point that reducing total > component cost may not lead to the lowest overall assembly cost. > > Bob Perlman > Cambrian Design Works > http://www.cambriandesign.com >Hi Bob, That's interesting. I've emailed some assembly folks I know, to see if I can get hold of how they price their work. If I get anywhere with it, I'll report back! Cheers, Syms.
Reply by ●March 5, 20072007-03-05
"Symon" <symon_brewer@hotmail.com> wrote> Hey Guys, > It's a been a while since we had a bypass capacitor religious war, so I > thought I'd stir things up a bit! > Seriously, I've been reading about X2Y capacitors, and a search of the > newsgroup revealed that these very interesting parts have only been > mentioned once or twice in passing. (By Austin, natch!) > > Check out :- > http://www.teraspeed.com/publications.html > Where they ask you to register for :- > http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf > > Steve Weir does a great job of showing why X2Y caps give you more bang for > your buck. As these parts have exceptionally low inductance, they can > substantially reduce the number of capacitors AND vias you need, and they > quote that :- > "Can replace from three to six+ regular caps depending on via and plane > geometries" > "Vias at $0.005/hole / $0.01 / capacitor typical, often COST MORE than the > capacitors they connect!" > > Here's another interesting article:- > http://www.x2y.com/bypass/mount/backside_cap.pdf > > They recommend using small 'puddles' of copper to connect all the bypass > elements together so you can use fewer capacitors but keep the same bypass > network performance. > > Check out http://www.x2y.com/bypass.htm for more articles. > > AFAICS, the main drawback is that X2Y caps are available in a range of > values. This means nutters will use several different values in their > bypass networks to create 'resonances' and the like. :-) > > Anyway, I hope this is of interest, Syms.BTW what about the LLM21 from Murata? 45pH for 4.7�F and not very expensive... http://www.murata.com/articles/ta0581.pdf http://www.murata.com/catalog/c02e.pdf (page 66) OK they are bigger (0805) than X2Y (0603) but 4.7�F seems interesting. Marc
Reply by ●March 6, 20072007-03-06
"Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message news:NKqdnUIskK8lO3HYnZ2dneKdnZydnZ2d@giganews.com...> > "Symon" <symon_brewer@hotmail.com> wrote >> >> Check out :- >> http://www.teraspeed.com/publications.html >> Where they ask you to register for :- >> http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf >> > > BTW what about the LLM21 from Murata? 45pH for 4.7�F and not very > expensive... > > http://www.murata.com/articles/ta0581.pdf > http://www.murata.com/catalog/c02e.pdf (page 66) > > OK they are bigger (0805) than X2Y (0603) but 4.7�F seems interesting. > > Marc >Hi Marc, The article above explains why the physical geometry of X2Y is superior to the reverse geometry part you mention. It's all to do with circles that have arrows on them! :-) The reverse geometry parts are good, but make sure the vias are at the ends of the part. (pg.17) Also, be careful of worring about capacitance rather than inductance. Here's an example:- Let's say we have a 100 MHz clocked system where stuff only happens on the rising edge. We'll say our dynamic current (the current used when switching) is 1A. OK, so on each switch of the clock the circuit uses 1A / 100MHz = 10nC. Q=CV, so the ripple this causes on your 4.7U capacitor is about 2mV. Very good. OK, let's say the circuit being run has a 2ns rise time. So, let's say on each switch, for 1ns the current is increasing, and for the next ns it's decreasing. Let's say (for ease of calculation) the current rises and falls linearly at equal rates so the current vs. time graph is an isosceles triangle with a base of 2ns. The area under this triangle represents our 10nC from above. So, the triangle is 10 amps high! Now, V = L dI/dt , dI/dt = 10A / 1 ns = 10 GA/s (!!) and, even ignoring the via and mounting inductance but using your figure of 45pH for the inductor, the ripple voltage due to the capacitor inductance, V = 0.45V. So, the noise from the inductance is about 200 times the noise from the capacitor discharging! You can see that buying cheaper capacitors with less capacititance isn't going to change things very much. (Except the change in your pocket! Ho, ho!) However, fitting two caps will almost halve the problem. HTH, Syms. p.s. I realise this is a simplistic model, but I hope it illustrates the point. And please correct my arithmetic if needed!
Reply by ●March 6, 20072007-03-06
"Symon" <symon_brewer@hotmail.com> wrote > "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message>> >> "Symon" <symon_brewer@hotmail.com> wrote >>> >>> Check out :- >>> http://www.teraspeed.com/publications.html >>> Where they ask you to register for :- >>> http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf >>> >> >> BTW what about the LLM21 from Murata? 45pH for 4.7�F and not very >> expensive... >> >> http://www.murata.com/articles/ta0581.pdf >> http://www.murata.com/catalog/c02e.pdf (page 66) >> >> OK they are bigger (0805) than X2Y (0603) but 4.7�F seems interesting. >> >> Marc >> > Hi Marc, > The article above explains why the physical geometry of X2Y is superior to > the reverse geometry part you mention. It's all to do with circles that > have arrows on them! :-) The reverse geometry parts are good, but make > sure the vias are at the ends of the part. (pg.17)I was not showing reverse geometry parts but IDC ones. They have 10 pins instead on the usual 8 and the inductance is 2 times lower than 8 pins IDC caps. In the paper you mention, they are page 17 except that these ones use 10 instead of 8 vias. As in page 25 it is said that they 8 pins IDC are equivalent to X2Y and as 10 pins IDC are 2 times better that 8 pins ones, it seems that the 10 pins IDC should be 2 times better than X2Y. Another links with lots of infos and measurements: http://home.att.net/~istvan.novak/papers/DC05_TF7.pdf http://home.att.net/~istvan.novak/papers/DC05East_TFMP2_v1.pdf The first one even has a proadlizer test showing it not that good in decoupling mode.> Also, be careful of worring about capacitance rather than inductance. > Here's an example:- > > Let's say we have a 100 MHz clocked system where stuff only happens on the > rising edge. We'll say our dynamic current (the current used when > switching) is 1A. OK, so on each switch of the clock the circuit uses 1A / > 100MHz = 10nC. Q=CV, so the ripple this causes on your 4.7U capacitor is > about 2mV. Very good. > OK, let's say the circuit being run has a 2ns rise time. So, let's say on > each switch, for 1ns the current is increasing, and for the next ns it's > decreasing. Let's say (for ease of calculation) the current rises and > falls linearly at equal rates so the current vs. time graph is an > isosceles triangle with a base of 2ns. The area under this triangle > represents our 10nC from above. So, the triangle is 10 amps high! Now, V = > L dI/dt , dI/dt = 10A / 1 ns = 10 GA/s (!!) and, even ignoring the via and > mounting inductance but using your figure of 45pH for the inductor, the > ripple voltage due to the capacitor inductance, V = 0.45V.Good point and scary numbers ;-). In fact past the cap resonance, you only see the ESL. But this also means that a bigger chip is as good as a smaller one for decoupling in the high frequencies region and much better in the lower ones so you can put a smaller number of bigger ones. Here are some X2Y measurements showing this: http://www.yageo.com/products/presentations/X2Y%20measurement%202006.pdf The question is which part has the lowest inductance. IMO it's the 10 vias ones.> So, the noise from the inductance is about 200 times the noise from the > capacitor discharging! You can see that buying cheaper capacitors with > less capacititance isn't going to change things very much. (Except the > change in your pocket! Ho, ho!) However, fitting two caps will almost > halve the problem.Anyway my pockets are already empty after paying for some big FPGAs and QDR memories. ;-)> HTH, Syms. > p.s. I realise this is a simplistic model, but I hope it illustrates the > point. And please correct my arithmetic if needed!Seems good for me. Marc
Reply by ●March 6, 20072007-03-06
"Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message news:V7-dnTN5P_L59HDYRVnygwA@giganews.com...> > > I was not showing reverse geometry parts but IDC ones. They have 10 pins > instead on the usual 8 and the inductance is 2 times lower than 8 pins IDC > caps. In the paper you mention, they are page 17 except that these ones > use 10 instead of 8 vias. As in page 25 it is said that they 8 pins IDC > are equivalent to X2Y and as 10 pins IDC are 2 times better that 8 pins > ones, it seems that the 10 pins IDC should be 2 times better than X2Y. > > Another links with lots of infos and measurements: > http://home.att.net/~istvan.novak/papers/DC05_TF7.pdf > http://home.att.net/~istvan.novak/papers/DC05East_TFMP2_v1.pdf > > The first one even has a proadlizer test showing it not that good in > decoupling mode. >Right, seems logical! Apologies, I misread the Murata part number and came to the reverse geometry ones first. Doh! So, yes, those interdigitated ones are pretty damn good too. Of course, you can fit more small parts in the same space as some big ones, so there's a trade off somewhere. Two parallel caps have about half the inductance of one big one. The papers are interesting too, thanks. Looks like the proadlizer is good for some things, but bypassing parts without on-board capacitance is not one of those things, as Mr. Weir said in his post.> > In fact past the cap resonance, you only see the ESL. But this also means > that a bigger chip is as good as a smaller one for decoupling in the high > frequencies region and much better in the lower ones so you can put a > smaller number of bigger ones. >OK, but again bearing in mind you can fit more small ones into the same space to reduce inductance.> > Here are some X2Y measurements showing this: > http://www.yageo.com/products/presentations/X2Y%20measurement%202006.pdf > > > The question is which part has the lowest inductance. IMO it's the 10 vias > ones. >Yep, they're a good solution also. Thanks for some interesting postings! Cheers, Syms.
