Port mapping a Verilog component in a VHDL design

Dear Sir or Madam,

I have the following problem:

I have a simulation component which is written in Verilog (not a trivial one
which could be translated to VHDL).
My toplevel design and all other components are written in VHDL.

My question:

Is it possible to include this Verilog component in my VHDL top level ?

What about the types  std_logic / std_logic_vector ?
Can I connect the inputs and outputs of the Verilog component to signals of
these types ?
How do I define it in the VHDL top level ?

I do not know if such thing is possible but I would be very
thankful for any information about that.


Kind regards
Andr�s V�zquez
G&D System Development

Mixed designs are supported by certain vendor tools. Modelsim SE has an
integrated kernel. See http://www.model.com/products/pdf/datasheets/se.pdf
page 2 for details.

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0401150750.76d8893a@posting.google.com...
> Dear Sir or Madam,
>
> I have the following problem:
>
> I have a simulation component which is written in Verilog (not a trivial
one
> which could be translated to VHDL).
> My toplevel design and all other components are written in VHDL.
>
> My question:
>
> Is it possible to include this Verilog component in my VHDL top level ?
>
> What about the types  std_logic / std_logic_vector ?
> Can I connect the inputs and outputs of the Verilog component to signals
of
> these types ?
> How do I define it in the VHDL top level ?
>
> I do not know if such thing is possible but I would be very
> thankful for any information about that.
>
>
> Kind regards
> Andr&#4294967295;s V&#4294967295;zquez
> G&D System Development

I've had some success dealing with customer's simulators that don't support
mixed languages by using the mapped output from synplicity in the target
language for simulation.  It is not as fast, and I have occasionally had
problems with INIT= attributes passing through if other than the default, but
otherwise it works.

fabbl wrote:

> Mixed designs are supported by certain vendor tools. Modelsim SE has an
> integrated kernel. See http://www.model.com/products/pdf/datasheets/se.pdf
> page 2 for details.
>
> "ALuPin" <ALuPin@web.de> wrote in message
> news:b8a9a7b0.0401150750.76d8893a@posting.google.com...
> > Dear Sir or Madam,
> >
> > I have the following problem:
> >
> > I have a simulation component which is written in Verilog (not a trivial
> one
> > which could be translated to VHDL).
> > My toplevel design and all other components are written in VHDL.
> >
> > My question:
> >
> > Is it possible to include this Verilog component in my VHDL top level ?
> >
> > What about the types  std_logic / std_logic_vector ?
> > Can I connect the inputs and outputs of the Verilog component to signals
> of
> > these types ?
> > How do I define it in the VHDL top level ?
> >
> > I do not know if such thing is possible but I would be very
> > thankful for any information about that.
> >
> >
> > Kind regards
> > Andr&#4294967295;s V&#4294967295;zquez
> > G&D System Development

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

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