Re: Multiplication operation

First, to address the question, you're not really doing multiplication but 
performing division through multiplication with decimals.  ISE doesn't do 
division either way.  Like John_H said, scale your numbers up (refer to fixed 
point numbers) so multiplication is done with integers.  When done, just 
scale the result down by the same amount for the final answer.  A hint is 
to scale the numbers by a power of 2 so you just have to do bit shifts.

Second, I would like to give my two cents on John_H's 1990's attitude.  You 
shouldn't tell someone to read up on vendor specific blocks when it is clear 
that they are just starting out, doesn't need an optimal implementation, 
and don't have a firm grasp on the basics.  You should give them a very simple 
and concise explanation at their level and a fix at their level.  The synthesizer 
is more than capable of handling the * symbol, the OP doesn't need to worry 
about what Xilinx puts on the hood.  If Xilinx were smart and had good programmers, 
which it seems they are trying to work towards, no one would need to know 
of any of the blocks under the hood.  People should be able to "program" 
the hardware.  The synthesis program should be smart enough to use the blocks 
under the hood to provide a near optimal implementation of the "program". 
 There is a reason why people use high level programming languages not assembly. 
 For everyone's sake, "designing" a system on an FPGA shouldn't be hard.


---Matthew Hicks


> VHDL_HELP wrote:
> 
>> Hi every body ,
>> i hope that you can help me , i want to do this operation:
>> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
>> when i check the syntax , i have these errors
>> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
>> can
>> not have such operands in this context.
>> ---------------------------------------------------------------------
>> ---------------------------------------------------------------------
>> ----------------------
>> 
>> library IEEE;
>> 
>> use IEEE.STD_LOGIC_1164.ALL;
>> 
>> use IEEE.STD_LOGIC_ARITH.ALL;
>> 
>> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>> 
>> entity operation is
>> Port ( clk : in  STD_LOGIC;
>> c1 : in  STD_LOGIC_VECTOR (7 downto 0);
>> c2 : in  STD_LOGIC_VECTOR (7 downto 0);
>> c 3: in  STD_LOGIC_VECTOR (7 downto 0);
>> s: out  STD_LOGIC_VECTOR (7 downto 0);
>> end operation;
>> 
>> architecture Behavioral of operation is
>> 
>> begin
>> 
>> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;
>> 
>> end Behavioral;
>> 
>> ---------------------------------------------------------------------
>> ---------------------------------------------------------------------
>> ----------------
>> 
>> and thanks for your help
>> 
> Can you tell me how the synthesizer will format your floating point
> result in s so it maps to silicon?
> 
> Use scaled integers.  Use the precision available in the hardware
> multipliers to get a rather precise approximation of s.  The digital
> realm is binary, after all, not decimal.
> 
> Please read up on how the hardware multipliers perform and how best to
> utilize them.  It's insanely sad to see someone trying to "program" an
> FPGA rather than design it.
> 

On 4 mar, 21:12, Matthew Hicks <mdhic...@uiuc.edu> wrote:
> First, to address the question, you're not really doing multiplication but
> performing division through multiplication with decimals.  ISE doesn't do
> division either way.  Like John_H said, scale your numbers up (refer to fixed
> point numbers) so multiplication is done with integers.  When done, just
> scale the result down by the same amount for the final answer.  A hint is
> to scale the numbers by a power of 2 so you just have to do bit shifts.
>
> Second, I would like to give my two cents on John_H's 1990's attitude.  You
> shouldn't tell someone to read up on vendor specific blocks when it is clear
> that they are just starting out, doesn't need an optimal implementation,
> and don't have a firm grasp on the basics.  You should give them a very simple
> and concise explanation at their level and a fix at their level.  The synthesizer
> is more than capable of handling the * symbol, the OP doesn't need to worry
> about what Xilinx puts on the hood.  If Xilinx were smart and had good programmers,
> which it seems they are trying to work towards, no one would need to know
> of any of the blocks under the hood.  People should be able to "program"
> the hardware.  The synthesis program should be smart enough to use the blocks
> under the hood to provide a near optimal implementation of the "program".
>  There is a reason why people use high level programming languages not assembly.
>  For everyone's sake, "designing" a system on an FPGA shouldn't be hard.
>
> ---Matthew Hicks
>
> > VHDL_HELP wrote:
>
> >> Hi every body ,
> >> i hope that you can help me , i want to do this operation:
> >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
> >> when i check the syntax , i have these errors
> >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
> >> can
> >> not have such operands in this context.
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------------
>
> >> library IEEE;
>
> >> use IEEE.STD_LOGIC_1164.ALL;
>
> >> use IEEE.STD_LOGIC_ARITH.ALL;
>
> >> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> >> entity operation is
> >> Port ( clk : in  STD_LOGIC;
> >> c1 : in  STD_LOGIC_VECTOR (7 downto 0);
> >> c2 : in  STD_LOGIC_VECTOR (7 downto 0);
> >> c 3: in  STD_LOGIC_VECTOR (7 downto 0);
> >> s: out  STD_LOGIC_VECTOR (7 downto 0);
> >> end operation;
>
> >> architecture Behavioral of operation is
>
> >> begin
>
> >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;
>
> >> end Behavioral;
>
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------
>
> >> and thanks for your help
>
> > Can you tell me how the synthesizer will format your floating point
> > result in s so it maps to silicon?
>
> > Use scaled integers.  Use the precision available in the hardware
> > multipliers to get a rather precise approximation of s.  The digital
> > realm is binary, after all, not decimal.
>
> > Please read up on how the hardware multipliers perform and how best to
> > utilize them.  It's insanely sad to see someone trying to "program" an
> > FPGA rather than design it.

hi , thank you for your advices first of all ,
then my equation to resolv is :
y=0.299 * R + 0.587 *G + 0.114 * B
for me what i tried to do is:
 
--------------------------------------------------------------------------------------------------------------------
entity rgb is
    Port ( clk : in  STD_LOGIC;
           R : in  STD_LOGIC_VECTOR (7 downto 0);
           G : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           Y : out  STD_LOGIC_VECTOR (31 downto 0);
           Cr : out  STD_LOGIC_VECTOR (31 downto 0);
           Cb : out  STD_LOGIC_VECTOR (31 downto 0));
end rgb;

architecture arch_rgb of rgb is
signal yreg :  STD_LOGIC_VECTOR (31 downto 0);
begin
process (clk)
	begin

	if clk='1' and clk'event then
		yreg <=  "00111110100110010001011010000111" * R +
"00111111000101100100010110100001"* G +
"00111101111010010111100011010100"* B;
		Y <= yreg;

							end if;
		end process;
end arch_rgb;

---------------------------------------------------------------------------------------------

On 4 mar, 21:12, Matthew Hicks <mdhic...@uiuc.edu> wrote:
> First, to address the question, you're not really doing multiplication but
> performing division through multiplication with decimals.  ISE doesn't do
> division either way.  Like John_H said, scale your numbers up (refer to fixed
> point numbers) so multiplication is done with integers.  When done, just
> scale the result down by the same amount for the final answer.  A hint is
> to scale the numbers by a power of 2 so you just have to do bit shifts.
>
> Second, I would like to give my two cents on John_H's 1990's attitude.  You
> shouldn't tell someone to read up on vendor specific blocks when it is clear
> that they are just starting out, doesn't need an optimal implementation,
> and don't have a firm grasp on the basics.  You should give them a very simple
> and concise explanation at their level and a fix at their level.  The synthesizer
> is more than capable of handling the * symbol, the OP doesn't need to worry
> about what Xilinx puts on the hood.  If Xilinx were smart and had good programmers,
> which it seems they are trying to work towards, no one would need to know
> of any of the blocks under the hood.  People should be able to "program"
> the hardware.  The synthesis program should be smart enough to use the blocks
> under the hood to provide a near optimal implementation of the "program".
>  There is a reason why people use high level programming languages not assembly.
>  For everyone's sake, "designing" a system on an FPGA shouldn't be hard.
>
> ---Matthew Hicks
>
> > VHDL_HELP wrote:
>
> >> Hi every body ,
> >> i hope that you can help me , i want to do this operation:
> >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
> >> when i check the syntax , i have these errors
> >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
> >> can
> >> not have such operands in this context.
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------------
>
> >> library IEEE;
>
> >> use IEEE.STD_LOGIC_1164.ALL;
>
> >> use IEEE.STD_LOGIC_ARITH.ALL;
>
> >> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> >> entity operation is
> >> Port ( clk : in  STD_LOGIC;
> >> c1 : in  STD_LOGIC_VECTOR (7 downto 0);
> >> c2 : in  STD_LOGIC_VECTOR (7 downto 0);
> >> c 3: in  STD_LOGIC_VECTOR (7 downto 0);
> >> s: out  STD_LOGIC_VECTOR (7 downto 0);
> >> end operation;
>
> >> architecture Behavioral of operation is
>
> >> begin
>
> >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;
>
> >> end Behavioral;
>
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------
>
> >> and thanks for your help
>
> > Can you tell me how the synthesizer will format your floating point
> > result in s so it maps to silicon?
>
> > Use scaled integers.  Use the precision available in the hardware
> > multipliers to get a rather precise approximation of s.  The digital
> > realm is binary, after all, not decimal.
>
> > Please read up on how the hardware multipliers perform and how best to
> > utilize them.  It's insanely sad to see someone trying to "program" an
> > FPGA rather than design it.

this program is with syntax correct but not synthetisable , what i
tried to d ois to convert the reals with binary ones

Matthew let me argue for peace:
It all depends on your roots.
If you started out as a logic designer (like I did), then you see the
FPGA as a wonderful way to design a production-worthy breadboard of
terrific complexity and very good performance. God's gift to the logic
designer, good-bye wire-wrap!
I think in terms of block diagrams, and use VHDL/Verilog to manage the
design process. I would never be in doubt about the choice of binary
vs decimal, or fixed vs floating point, because they have such
enenormous impact on the design efficiency.

If you start out as a computer programmer, then you design=program the
way this thread was started, totally oblivious of hardware constraints
and limittions. Let the synthesizer worry about those details! The
trouble is that these unworthy details can impact the design by an
order of magnitude in size=cost and performance.

You will never beat the urge for economy, performance, and design
elegance out of us hardware guys. Maybe one day FPGAs will become so
big and cheap and fast that it does not matter anymore.
Well, hopefully there will always be Social Security.
And St. Peter might show mercy with us former pip-pokers genus
schemato-saurus.
Peter Alfke


On Mar 4, 12:12 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote:
> First, to address the question, you're not really doing multiplication but
> performing division through multiplication with decimals.  ISE doesn't do
> division either way.  Like John_H said, scale your numbers up (refer to fixed
> point numbers) so multiplication is done with integers.  When done, just
> scale the result down by the same amount for the final answer.  A hint is
> to scale the numbers by a power of 2 so you just have to do bit shifts.
>
> Second, I would like to give my two cents on John_H's 1990's attitude.  You
> shouldn't tell someone to read up on vendor specific blocks when it is clear
> that they are just starting out, doesn't need an optimal implementation,
> and don't have a firm grasp on the basics.  You should give them a very simple
> and concise explanation at their level and a fix at their level.  The synthesizer
> is more than capable of handling the * symbol, the OP doesn't need to worry
> about what Xilinx puts on the hood.  If Xilinx were smart and had good programmers,
> which it seems they are trying to work towards, no one would need to know
> of any of the blocks under the hood.  People should be able to "program"
> the hardware.  The synthesis program should be smart enough to use the blocks
> under the hood to provide a near optimal implementation of the "program".
>  There is a reason why people use high level programming languages not assembly.
>  For everyone's sake, "designing" a system on an FPGA shouldn't be hard.
>
> ---Matthew Hicks
>
> > VHDL_HELP wrote:
>
> >> Hi every body ,
> >> i hope that you can help me , i want to do this operation:
> >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
> >> when i check the syntax , i have these errors
> >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
> >> can
> >> not have such operands in this context.
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------------
>
> >> library IEEE;
>
> >> use IEEE.STD_LOGIC_1164.ALL;
>
> >> use IEEE.STD_LOGIC_ARITH.ALL;
>
> >> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> >> entity operation is
> >> Port ( clk : in  STD_LOGIC;
> >> c1 : in  STD_LOGIC_VECTOR (7 downto 0);
> >> c2 : in  STD_LOGIC_VECTOR (7 downto 0);
> >> c 3: in  STD_LOGIC_VECTOR (7 downto 0);
> >> s: out  STD_LOGIC_VECTOR (7 downto 0);
> >> end operation;
>
> >> architecture Behavioral of operation is
>
> >> begin
>
> >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;
>
> >> end Behavioral;
>
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------
>
> >> and thanks for your help
>
> > Can you tell me how the synthesizer will format your floating point
> > result in s so it maps to silicon?
>
> > Use scaled integers.  Use the precision available in the hardware
> > multipliers to get a rather precise approximation of s.  The digital
> > realm is binary, after all, not decimal.
>
> > Please read up on how the hardware multipliers perform and how best to
> > utilize them.  It's insanely sad to see someone trying to "program" an
> > FPGA rather than design it.

On Sun, 04 Mar 2007 12:47:23 -0800, Peter Alfke wrote:

> If you started out as a logic designer (like I did), then you see the
> FPGA as a wonderful way to design a production-worthy breadboard of
> terrific complexity and very good performance. 
> ...
> If you start out as a computer programmer, then you design=program the
> way this thread was started, totally oblivious of hardware constraints
> and limittions. 
> ...
> You will never beat the urge for economy, performance, and design
> elegance out of us hardware guys. 
> ...

So where do us embedded systems half-breeds who have done both rank in
this comparison?  One could postulate that we get 95% of the efficiency
of the purebred HW and purebred programmer (rejecting the urge to try for
that last 5% which takes all the time), beating you both to market with a
design which is elegant, economical, and meets performance requirements
since we see from both sides.

   :-P     ;-))


     ~Dave~

Dave wrote:
> On Sun, 04 Mar 2007 12:47:23 -0800, Peter Alfke wrote:
> 
>> If you started out as a logic designer (like I did), then you see the
>> FPGA as a wonderful way to design a production-worthy breadboard of
>> terrific complexity and very good performance. 
>> ...
>> If you start out as a computer programmer, then you design=program the
>> way this thread was started, totally oblivious of hardware constraints
>> and limittions. 
>> ...
>> You will never beat the urge for economy, performance, and design
>> elegance out of us hardware guys. 
>> ...
> 
> So where do us embedded systems half-breeds who have done both rank in
> this comparison?  One could postulate that we get 95% of the efficiency
> of the purebred HW and purebred programmer (rejecting the urge to try for
> that last 5% which takes all the time), beating you both to market with a
> design which is elegant, economical, and meets performance requirements
> since we see from both sides.
> 
>    :-P     ;-))
> 
> 
>      ~Dave~

You go, Dave!
Being in this middle ground - in my opinion - give you exceptional 
insight into strong designs with better time to completion.

A programmer can become hardware aware and cross over enough to get the 
performance.  A hardware guy can get deep enough into the computing side 
to increase the algorithmic efficiency of the design.  It sounds like 
you're already squarely placed in this productive center.

This is one of the few threads that got better as it went on.
Rare excepton...
Peter Alfke

On Mar 4, 7:51 pm, John_H <newsgr...@johnhandwork.com> wrote:
> Dave wrote:
> > On Sun, 04 Mar 2007 12:47:23 -0800, Peter Alfke wrote:
>
> >> If you started out as a logic designer (like I did), then you see the
> >> FPGA as a wonderful way to design a production-worthy breadboard of
> >> terrific complexity and very good performance.
> >> ...
> >> If you start out as a computer programmer, then you design=program the
> >> way this thread was started, totally oblivious of hardware constraints
> >> and limittions.
> >> ...
> >> You will never beat the urge for economy, performance, and design
> >> elegance out of us hardware guys.
> >> ...
>
> > So where do us embedded systems half-breeds who have done both rank in
> > this comparison?  One could postulate that we get 95% of the efficiency
> > of the purebred HW and purebred programmer (rejecting the urge to try for
> > that last 5% which takes all the time), beating you both to market with a
> > design which is elegant, economical, and meets performance requirements
> > since we see from both sides.
>
> >    :-P     ;-))
>
> >      ~Dave~
>
> You go, Dave!
> Being in this middle ground - in my opinion - give you exceptional
> insight into strong designs with better time to completion.
>
> A programmer can become hardware aware and cross over enough to get the
> performance.  A hardware guy can get deep enough into the computing side
> to increase the algorithmic efficiency of the design.  It sounds like
> you're already squarely placed in this productive center.

VHDL_HELP wrote:
> 
> hi , thank you for your advices first of all ,
> then my equation to resolv is :
> y=0.299 * R + 0.587 *G + 0.114 * B
> for me what i tried to do is:
>  
> --------------------------------------------------------------------------------------------------------------------
> entity rgb is
>     Port ( clk : in  STD_LOGIC;
>            R : in  STD_LOGIC_VECTOR (7 downto 0);
>            G : in  STD_LOGIC_VECTOR (7 downto 0);
>            B : in  STD_LOGIC_VECTOR (7 downto 0);
>            Y : out  STD_LOGIC_VECTOR (31 downto 0);
>            Cr : out  STD_LOGIC_VECTOR (31 downto 0);
>            Cb : out  STD_LOGIC_VECTOR (31 downto 0));
> end rgb;
> 
> architecture arch_rgb of rgb is
> signal yreg :  STD_LOGIC_VECTOR (31 downto 0);
> begin
> process (clk)
> 	begin
> 
> 	if clk='1' and clk'event then
> 		yreg <=  "00111110100110010001011010000111" * R +
> "00111111000101100100010110100001"* G +
> "00111101111010010111100011010100"* B;
> 		Y <= yreg;
> 
> 							end if;
> 		end process;
> end arch_rgb;
> 
> ---------------------------------------------------------------------------------------------
 >
 > this program is with syntax correct but not synthetisable , what i
 > tried to d ois to convert the reals with binary ones

First, I'm worried you might not have the right VHDL libraries specified 
for your operation.

I'd suggest you

1) do a sample module with just one multiply, keeping the binary value 
to 17 bits.  If the one multiply - no addition - doesn't work, it's 
quite possibly a VHDL library issue.  I just know that they're touchy - 
I'm a Verilog guy myself, not VHDL.

2) if the one equation works, define intermediate values for your scaled 
R, scaled G, and scaled B.  Then add those scaled values together to get 
your result.

3) consider whether VHDL will have a problem assigning a nominally 
42-bit result to a 32-bit vector and give you synthesis problems if the 
results don't match in size.


Please keep in mind that multiplication with real numbers is abstracted 
in hardware.  When it's time to implement the operation, there are 
issues with precision and error that have to be understood whether 
you're using an 8-bit ALU or a dual-precision floating point unit.  You 
will have error.  The synthesizer doesn't know what to do with the error 
- round up? round down? truncate? do something else? - and you must 
decide what to do to make your math work out.  If you're in an 8-bit 
ALU, you can do operations that are much more precise than 8 bits.  You 
could cascade multiply/shift/add operations to get 8x24 bit multiplies, 
for instance.

Most of the Xilinx families can multiply 17-bit unsinged values using 
embedded multipliers.  Multiplying an 8-bit color value by a 32-bit 
constant seems like a bit of overkill.  Should the synthesizer perform 
two multiplies and add the intermediate results together to give you a 
40 bit result?  Perhaps.  Personally, I'm glad the synthesis doesn't try 
to implement things this way.

I suggested you "know your silicon" not because everyone using the FPGAs 
should become a down-in-the-transistors hardware guy but because the 
dedicated resources which will implement this rather resource-intensive 
operation has specifications on how it operates, just like the 
arithmetic units in a microprocessor or the single-precision real 
operation in the C language.

Bottom line: since math in many cases is an abstraction, you have to 
know how abstract your results will be.

"VHDL_HELP" <abaidik@gmail.com> wrote in message 
news:1173116345.883356.301410@30g2000cwc.googlegroups.com...
<snip>

> -- how to get cr
> crr <=  r
> crg <=  "0110101101" * g;  -----> it told me that there is an error here

<snip>

> cbb <=  b
> cb1 <= cbb - cbr - cbg; -----> it told me that there is an error here

<snip>
> ------------------------------------------------------------------------------------------------
> it is the error for the 2lines: parse error, unexpected IDENTIFIER,
> expecting SEMICOLON
> i hope that you can help me , please i  m really a beginner
> thank you


Look at the lines above where the error is flagged.
You need to have a semicolon (;) after the crr <= r and the cbb <= b lines. 

On 5 mar, 19:01, "John_H" <newsgr...@johnhandwork.com> wrote:
> "VHDL_HELP" <abai...@gmail.com> wrote in message
>
> news:1173116345.883356.301410@30g2000cwc.googlegroups.com...
> <snip>
>
> > -- how to get cr
> > crr <=3D  r
> > crg <=3D  "0110101101" * g;  -----> it told me that there is an error h=
ere
>
> <snip>
>
> > cbb <=3D  b
> > cb1 <=3D cbb - cbr - cbg; -----> it told me that there is an error here
>
> <snip>
>
> > -----------------------------------------------------------------------=
----=AD---------------------
> > it is the error for the 2lines: parse error, unexpected IDENTIFIER,
> > expecting SEMICOLON
> > i hope that you can help me , please i  m really a beginner
> > thank you
>
> Look at the lines above where the error is flagged.
> You need to have a semicolon (;) after the crr <=3D r and the cbb <=3D b =
lines.

thanks you , it really was a very small mistake and i didnt got it
thank you